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I'm working on understand ADC specifications a little bit better and I'm stuck on the topic of settling time.

I'm reading an App Note from Texas Instruments which talks about the settling time of the switched capacitor in the input of a ADC.

However for some reason I cannot quite understand, they talk about settling to within 1/16th of an LSB in the acquisition time to get some required accuracy figure.

The required input time constant must be small enough to be within the given ADC analog input sampling time (Ts) for the desired accuracy. In the case given in Section 4, 1/16 LSB was chosen to give an error of not more than 6.25%.

This is the bit I'm having trouble with:

  • How does 1/16 LSB get you to 6.25% error.
  • Surely as long as the input caps settle to within 1 LSB then you can't get more accurate than that?
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    \$\begingroup\$ 6.25% of one LSB, not of full scale. \$\endgroup\$
    – Spehro 'speff' Pefhany
    Commented Oct 14, 2021 at 13:21
  • \$\begingroup\$ sure you can have the outcome settle to more accuracy within 1LSB. Anywhere from 0 to 1LSB is 'within' 1LSB. Guaranteeing less settling within less than an LSB allows budgeting for other errors (such as DNL/INL) besides settling. \$\endgroup\$
    – pat
    Commented Oct 15, 2021 at 8:10

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Section 2.1 of the linked document explains their rationale for using 1/16th LSB as the target time for settling.

The author set the total conversion error target as +/- 1/2LSB including other errors such as DNL and INL. The allowable error budget for settling is assumed to be 0.1LSB that they have rounded down to 1/16th for the rest of the calculations.

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  • \$\begingroup\$ This is exactly what I missed, I hadn't realised they were also budgeting for the other error sources in the ADC. Thanks! \$\endgroup\$
    – VBwhatnow
    Commented Oct 15, 2021 at 9:57

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