Effect of impedance on noise immunity

Question

I read an introduction for the CMOS inverter from [1], and it mentions: "In steady state, there always exists a path with finite resistance between the output and either VDD or GND. A well-designed CMOS inverter, therefore, has a low output impedance, which makes it less sensitive to noise and disturbances".

I don't understand how the low output impedance influence the noise of the inverter. If the inverter directly links to a transistor, does the low impedance of the inverter still help the noise immunity?

[1] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolić. Digital integrated circuits: a design perspective, volume 7. Pearson education Upper Saddle River, NJ, 2003.

Answer 1

If some disturbance causes a current in the inverter output node, this current will seek to spread across the system capacitance, so it usually flows into high capacitance nodes such as GND or VDD. The impedance overcome by this current causes a corresponding voltage spike. Keeping the impedance small thus reduces the voltage spike and avoids spurious logic level crossing due to the interference.

Answer 2

"A well-designed CMOS inverter, therefore, has a low output impedance, which makes it less sensitive to noise and disturbances".

This is a bit misleading. A CMOS inverter's low output impedance does not affect the operation of the inverter itself. Rather the low output impedance makes it more difficult for noise to couple onto the output line, and so makes it less likely that the following devices would be upset by the coupled noise.

Think of this as a system thing - a system of two devices - rather than as a single device.

Here's another way to look at it. A signal line/trace on a PCB is much less sensitive to noise when it is actively driven than when it is resistively pulled up or down. And a trace is much less sensitive to noise when it is resistively pulled up or down than when it is left open - floating.