What would a transistor level design of an XOR gate look like?
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1\$\begingroup\$ hyperphysics.phy-astr.gsu.edu/hbase/electronic/or.html#c2 \$\endgroup\$– John RennieCommented Mar 15, 2013 at 14:53
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1\$\begingroup\$ The design of a logic gate doesn't fall under our scope, I think. I'm inclined to agree with @Qmechanic that this might go better on EE. \$\endgroup\$– David ZCommented Mar 15, 2013 at 17:15
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\$\begingroup\$ Possible duplicate: electronics.stackexchange.com/q/53142/17592 \$\endgroup\$– user17592Commented Mar 15, 2013 at 19:50
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\$\begingroup\$ The answer to this question depends on what kind of interfacing you want: how are logic levels represented on the inputs and outputs. \$\endgroup\$– KazCommented Mar 17, 2013 at 10:55
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Given XOR = /AB + A/B you can build it out of the following:
AND:
OR:
NOT:
But my favorite is:
where:
But the TG based design has limitations. You can't cascade them and must have a driven input and a CMOS load.
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\$\begingroup\$ In NMOS technology, if one needs an XOR gate and the inputs come from logic that isn't driving anything else, one could get by with two transistors and one passive pull-up: simply connect the drains of the two transistors to the pull-up, connect A to the source of one and gate of the other, and B to the remaining source and drain. Even if one had to add inverters before the XOR gate which served no purpose except to drive it, it would still be more compact than other realizations. I wonder if any NMOS chips used such a design? \$\endgroup\$– supercatCommented Mar 15, 2013 at 19:37
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\$\begingroup\$ @supercat My guess is: they must have, since most of those designs were done in the ruby-lith days, they'd be looking to minimize the # of transistors. \$\endgroup\$ Commented Mar 15, 2013 at 19:51
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\$\begingroup\$ It's possible that they did so, but in the schematics I've seen of NMOS devices XOR gates are implemented in other ways. \$\endgroup\$– supercatCommented Mar 15, 2013 at 20:02