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I'm using the following circuit with Q1 and R20 in order to detect 0-24V pulses that might exist on the V24_IN_S1 input: schematic diagram of the circuit

Before V24_IN_S1 there is the following circuit that transforms the 24V-level signals to lower ones: interface circuit

The idea is that the pulses are converted to 0-3.3V pulses that can be detected by the MCU (an ESP32-S3) that receives V24_IN_S1_BYPASS on one of its GPIOs.

At the same time, the (analogue) signal V24_IN_S1 is driven to multiplexer and then an ADC (not shown in the diagram). MUX_EN_N (active LOW) enables or disables the MUX outputs.

What I have observed is the following:

  • When MUX_EN_N is HIGH (MUX output disabled and pin 5 of U20 is connected to pin 6), then the V24_IN_S1_BYPASS signal is switching, following V24_IN_S1, but its LOW level is very high, therefore the MCU always sees a digital HIGH.

  • When MUX_EN_N is LOW (MUX output enabled and pin 5 of U20 is connected to pin 4), then the V24_IN_S1_BYPASS signal is switching as it should, and its LOW level is close to 0, enough so that the MCU can recognize the digital LOW levels.

Here is an oscilloscope capture that summarizes the situation (with green color it's V24_IN_S1 and with yellow color it's V24_IN_S2_BYPASS): scope capture

You can see that in the beginning (when MUX_EN_N is HIGH), V24_IN_S1_BYPASS doesn't go all the way down to 0V. This changes a little bit after 2.5 sec, when MUX_EN_N switches LOW for a period and V24_IN_S1_BYPASS switches close to 0V.

My problem is that it is very puzzling why there is this behavior. I cannot really understand how MUX_EN_N is affecting V24_IN_S1_BYPASS.

My first thought was that perhaps Q1 doesn't open completely when MUX_EN_N is HIGH (for some reason) and that causes a high Ron, with the result we observe. However, from the waveforms, I cannot see how this is possible because the V24_IN_S1 signal puts in all cases around 2.4V across G-S of Q1. In any case, when MUX_EN_N is HIGH, U20 connects V24_IN_S1 to pin 6, so to a floating node. Compared to being connected to the MUX input, I suppose this is a less complicated scenario (less capacitance for example), therefore I would expect a problem when MUX_EN_N is LOW, if anything.

The scenario that the GPIO of the MCU where V24_IN_S1_BYPASS is connected changes to something else than INPUT (e.g., OUTPUT or INPUT with internal pull-down) is not something very likely. In any case, I've studied the code running on the MCU and I didn't see anything like this.

Any good ideas why this can be happening? Can you see any logic behind it?

UPDATE 1: I've disconnected the V24_IN_S1_BYPASS signal from the MCU (by physically cutting the trace on the board) and I still observe the same behavior. I have at least ruled out that there is some issue with the GPIO and the MCU.

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  • \$\begingroup\$ Can we see a complete schematic? The DG4051 is cutoff. It also looks like you have two signals turning on at the same time. \$\endgroup\$
    – Voltage Spike
    Commented Oct 21 at 16:23
  • \$\begingroup\$ This is pretty much the whole schematic, when it comes to this specific function / signal. Additionally, the MUX2_COM_FLT is connected directly to one input of an I2C A/D converter (ADS1015). The whole board extends to multiple pages, but the rest is not relevant. Which two signals do you mean they turn on at the same time? \$\endgroup\$
    – nickagian
    Commented Oct 21 at 19:17

1 Answer 1

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As embarrassing as it can be, I have to post here the answer to the problem. It has nothing to do with the circuit or anything else.

The problem was that there was a GND connection missing in the layout, having as a result that the GND pin of the MOSFET is floating. This missing connection is true for a small GND island on the top layer, that also included two of the DG2012 switches. Therefore, the GND pin is "set" to a level of around 1.3V (I suspect through some internal diode connections in one of the three ICs), essentially, bringing the VGS of the MOSFET at levels that are not higher than VGSth.

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