Problem getting VHDL syntax correct

Question

I am trying to learn VHDL prior to returning to school. I have been using the text Digital Design with CPLD Applications and VHDL ISBN-13: 978-1401840303 Other references are: http://www.gmvhdl.com/VHDL.html and http://www.freerangefactory.org/dl/free_range_vhdl.pdf

What I am trying to accomplish is to create a project that will be used to program a cpld to be a standalone digital clock. The clockin pin of the cpld will be driven be a 2hz timebase from a 32768hz crystal divided down by a cmos 14bit ripple counter (HC4020). The cpld outputs will drive seven segment displays.

In order to make sure that I am learning important concepts, I am trying to implement this project as multiple entities that are connected together so that the block diagram is essentially identical to the Fig 8-10 in The TTl Cookbook. I have attempted to start with an example straight out of the Dueck text book and it will not compile:

—— bcd_7seg.vhd
—— BCD-to-seven-segment decoder
ENTITY bcd_7seg IS
PORT(
d3, d2, d1, d0 : IN BIT;
a, b, c, d, e, f, g : OUT BIT);
END bcd_7seg;
ARCHITECTURE seven_segment OF bcd_7seg IS
SIGNAL input : BIT_VECTOR (3 downto 0);
SIGNAL output: BIT_VECTOR (6 DOWNTO 0);
BEGIN
input <= d3 & d2 & d1 & d0;
WITH input SELECT
output <= “0000001” WHEN “0000”,
“1001111” WHEN “0001”,
“0010010” WHEN “0010”,
“0000110” WHEN “0011”,
“1001100” WHEN “0100”,
“0100100” WHEN “0101”,
“1100000” WHEN “0110”,
“0001111” WHEN “0111”,
“0000000” WHEN “1000”,
“0001100” WHEN “1001”,
“1111111” WHEN others;
—— Separate the output vector to make individual pin outputs.
a <= output(6);
b <= output(5);
c <= output(4);
d <= output(3);
e <= output(2);
f <= output(1);
g <= output(0);
END seven_segment;

text comments: Why not simply define d as a vector? If we wish to create a graphic symbol for the seven-segment decoder, the above method creates a symbol shown with four separate in- puts, rather than a single thick line for a 4-bit bus input. The design will work either way.

I am using Altera Quartus II 13.0.1 (an older version) as it supports the EPM7032slc44 which is cheap and plentiful from digikey. I have a logical devices chipmaster 6000xp to program parts. I have tried changing project settings in the ide to switch between vhdl 87 and vhdl 93 and this example still has several syntax errors. It is puzzling to me that the compiler only barks at the first few lines (14-19) of the select statements. I changed the ending commas to semicolons with no effect.

I have three things I wish to get clear on here: A The correct syntax for defining entity ports B The correct syntax for making architecture declarations on those ports C How do I go about making entity and architecture declarations for entity A that can be accessed by entity B regardless whether entity B uses std_logic vector(6 downto 0) or eight discrete lines eg a std_logic, b std_logic etc.

Thank you for your time to read and comment.

Answer 1

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.