I am currently working on converting a high level language into an equivalent circuit.. I am able to convert simple expressions like a+b, a.b or a combination of them using gates. But I wanted to know if there's a generic method to implement if-else statement using electronic components such as gates, mux, ff. A simple answer would be to use mux-demux. But that wouldn't solve the following problem(for example)



The construct for that would be positive edge triggered flip flop. So is there any general way to implement if-else statement?

Any help would be appreciated. Thanks!


2 Answers 2


For combinational logic, if/else is implemented as a 2:1 multiplexer. In Boolean algebra, this would be:

Q = (A * S) + (B * S')


  • S is the input fed by the if condition,
  • A is the input fed by the then subexpression,
  • B is the input fed by the else subexpression, and
  • Q is the output of the expression.

You could theoretically generalize this to include a single clock edge, but it gets a lot more complex and would resemble an FPGA cell when you're done. Basically, if a clock edge were included, you could not have an else clause (because it is implicitly "do not change the output"), and any non-edge parts of the if condition would simply become the clock enable expression. Once the dust settled, you'd be left with a less-clear version of the always_ff statement, which you should use instead anyway.

Conditions with two or more clock edges are not synthesizable.

EDIT: First, I'm not sure if(posedge(...)) is synthesizable. In general, you use the posedge(...) clause in the always_ff @(...) line and don't need the posedge() inside the block.

In SystemVerilog, the generic form of a 2:1 multiplexer is an if statement. For example:

always_comb begin
        Q = A;
        Q = B;

If there's a clock edge, though, you need to use a flip-flop:

always_ff @(posedge CLK) begin
        Q <= D;

Adding an asynchronous reset looks like this:

always_ff @(posedge RESET, posedge CLK) begin
        Q <= '0;
    else if(CLK_ENA)
        Q <= D;

In this case, RESET is active-high. Note that you only need to say RESET is edge sensitive in the @() part. In the rest of the block, RESET will have the level after the edge. Also note that the edge-sensitivities are a list; you can't say "and". (In original Verilog, you separated edge sensitivities with "or", misleading people into thinking "and" could work as well.)

  • \$\begingroup\$ hey thanks a lot for your reply!...however when I am generalizing what do I use as S ? ( i have a posedge(clk)...i.e an attribute of a signal and not a signal itself)....also could you kindly explain what do u meant by "any non edge part of if condition become clock enable expression"...thanks a lot! \$\endgroup\$ Jun 14, 2011 at 15:34
  • \$\begingroup\$ What do you mean by "^ ........"? \$\endgroup\$ Jun 14, 2011 at 16:39
  • \$\begingroup\$ I realized I hadn't tagged you in my reply to your comment...so I wrote another comment to direct you to the first one!...hence the ^ .... i used the remaining dots since a comment has to be longer than 15 characters :D ...anyway could you please solve my query ? \$\endgroup\$ Jun 14, 2011 at 17:16
  • \$\begingroup\$ An answerer gets notified of all comments to their answer, so I didn't miss you. You only need to use the tag if you were replying to a commenter. As to your queries, first, see the combinational example for where S is. Since you have an edge in your condition, you can't use combinational logic, and must use a flip-flop instead. As to your second query, see the flip flop example above. It could be thought of as if(CLK_ENA & posedge(CLK)); note that part of that condition is posedge() and part is not. \$\endgroup\$ Jun 14, 2011 at 20:40
  • \$\begingroup\$ thanks for the reply!..but how would you in general synthesize a code with more than one element in the sensitivity?..i mean having one element in the sensitivity list I can feed it to the clock..but what about two elements there?..I believe "reset idea" wont always work..and what if it is more than 2? Thanks!! \$\endgroup\$ Jun 18, 2011 at 14:39

Wouldn't this be a simple combination of an AND and XOR? AND has logic being tested and second is tied to high. XOR has logic being tested and second is tied high.


0 (1) = 0

1 (1) = 1


0 (1) = 1

1 (1) = 0

  • \$\begingroup\$ Strictly speaking, since else is a catch-all, wouldn't nand be more appropriate than xor? \$\endgroup\$ Nov 30, 2015 at 16:16

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