VHDL - Why does frequency divider counter max at one less than half period?

Question

In this tutorial on creating a frequency divider in VHDL, we transform a 50MHz input into a 200Hz output with a process that counts from 1 to 124999. The guide offers an explanation for why 124999 is chosen and not 250000, but I'm unclear as to why 124999 is chosen instead of 125000. I'm probably confused by some off-by-one counting issue, but I'd appreciate further explanation here. For reference, the discussion of the 124999 limit is reproduced below.

The frequency_divider process, lines 16 to 28, generates the 200Hz signal by using a counter from 1 to 124999. Why 124999 and not 250000? A clock signal is a square wave with a 50% of duty cycle (same time active and inactive); for this case, 125000 cycles active and 125000 cycles inactive. Since the counter begins at zero, the superior limit is 125000 - 1.

Answer 1

0 to 124999 is exactly 125000 counts. Starting at zero is a simple convention that can make some code a bit simpler (like working with lists and pointers), but it means that you increment to one less than the number of iterations you need.

Generally when you build a divider like this, you are interested in the half period so you can invert once every half period and get a waveform with a perfect 50% duty cycle.