For a project I am working on, I require a counter whose value increases as soon as the increment control goes high (i.e. on the rising edge). However, I have had trouble implementing this in VHDL.
Here is some code that I have written:
IF Reset='1' THEN count := 0; -- Asynchronous reset ELSIF rising_edge(clock) THEN IF Enable = '1' THEN count := count+1; -- Increment END IF; END IF; q <= std_logic_vector(to_unsigned(count,12));
Here is the ModelSim simulation waveform:
As you can see, 'q' is only updated one clock cycle AFTER the Enable input goes high. I want q to increment as soon as Enable goes high. Is there a way to do this?