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In Altium, I want to add via stitching on the ground pours. But the vias sometimes are placed on the designators. I don't want to adjust the designators on silk every time after stitching. So, is there any way to tell Altium not to do stitching on my designators, even on any object on my silkscreen?

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    \$\begingroup\$ From what I know, Altium doesn't do clearance checking between different layers. In any case, why would you let something like silkscreen influence the electrical performance of your design? I'd recommend that you enable via tenting and be done with it. \$\endgroup\$
    – Armandas
    Dec 24, 2015 at 11:20
  • \$\begingroup\$ Not all my boards are solder by machine, sometimes we need solder them by hands! The via can be tent sure, but it won't make them invisible, there will be a small hole at least, it "destroy" the designator silk, if the designator is small, make them difficult to read. So if Altium can do this cleverly, why not let it do? :) \$\endgroup\$
    – diverger
    Dec 24, 2015 at 16:11
  • \$\begingroup\$ @Amandas, Altium doesn't check copper clearance between copper layers, but there is a design rule to catch silkscreen over soldermask openings. \$\endgroup\$
    – The Photon
    Dec 24, 2015 at 17:19
  • \$\begingroup\$ @diverger, but you shouldn't need to solder to the stitching vias. If you tent holes up to 10 or 12 mils, it really doesn't produce much of a mark on the soldermask layer and shouldn't impact silkscreen much --- although some fabs might not like fully tented vias because entrapped air can (so I'm told) blow out the tenting sometimes when the board is heated. \$\endgroup\$
    – The Photon
    Dec 24, 2015 at 17:21

1 Answer 1

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This answer is twofold, answering these questions:

  1. Can you do it?
  2. Should you want to do it?

1. Can you do it?

You most probably can. In the Clearance Rules you can use the keyword "IsStitchingVia", or the parameter line "IsStitchingVia and InNet('{yourNetName}')" for a specific net for the first object and for the second object you can use "InLayer('{yourLayerName}')" and all kinds of specific keywords to find component labels.

But I have never tested whether this works with Silkscreen specifically, since: See 2.


2. Should you want to do it?

No. You should want to keep the stitching as perfect as your design allows, because if you have a need for stitching, you have a need for it to be good and as complete as possible.

Want to make sure your designators are still readable over a via in your stitch? You have them filled and tented. Or very tiny and tented will also often fill them with solder mask automatically - whether filled and tented or tiny and tented is cheaper depends on your fab, but it's extremely likely tiny and tented is cheaper these days.


Appendix: How to tent stitched vias

To fully tent your vias, in the "Add Stitching to Net" menu click the check-marks in front of "Force Complete tenting on Top" and "Force Complete tenting on Bottom". In Version 15 that's lower right, I seem to remember the same for 14, for 16 I don't know as I'm in a critical design and can't risk an update right now.

How to get the vias neatly filled is, as far as I know, asking the Fab what parameter to set and how, but to be honest, last design with Altium I had filled vias my colleague did that, making the last time I specifically requested them myself 2007, so I forgot. (It's possible he just phoned them to ask how small a via should be to guarantee it gets filled with solder mask when tented, to be honest)

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  • \$\begingroup\$ You'll get my up vote if you can post the exact queries to use with the clearance rule. \$\endgroup\$
    – Armandas
    Dec 24, 2015 at 13:22
  • \$\begingroup\$ @Armandas they are there. I don't know what you lot call your layers, so I cannot fill that in for you. Nor do I know what you put on the silkscreen with which properties. \$\endgroup\$
    – Asmyldof
    Dec 24, 2015 at 15:30
  • \$\begingroup\$ I dont' think you'd use a clearance rule. You'd use the silkscreen over soldermask opening rule. \$\endgroup\$
    – The Photon
    Dec 24, 2015 at 17:22
  • \$\begingroup\$ @ThePhoton But then it'll only highlight, right? The OP wanted to have no stiches because else move text. I mean, I've been dragging refdes and print around the majority of my life and happy to do it for proper design, but still... Question, answer. \$\endgroup\$
    – Asmyldof
    Dec 24, 2015 at 18:02
  • \$\begingroup\$ @Asmyldof How is an Electrical Clearance rule going to work with a silkscreen object? \$\endgroup\$
    – Armandas
    Dec 24, 2015 at 19:54

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