MOSFET fast turn-off not enough

Question

I have a PWM bridge driving a higher than 1k load from 200V supply. The simplified, equivalent schematic is this:

The drivers I'm using are slow turn-on/fast turn-off and, in the schematic, it's a 50% duty-rati.,The parasitics modeled here also involve some capacitance across the filtering inductor. These will cause some spikes, sure, but they pale compared to the switching problem and, while I can get away with 100-200mA peak, what I have here is a bit scary:

The driving, as seen here, is a much nicer version to what will be in reality. The problem is that the mid-point voltage, V(mid), doesn't fall with the ending of the commanding pulse, only with the rising of the complementary pulse, which makes it overlap a bit and cause a spike, in addition to the inevitable parasitic. Here's a zoomed-in portion:

You can see that the upper drive, V(gh,mid), is turned off fast and has plenty of dead-time, while V(mid) keeps on going until V(gl) starts.

I know there are circuits trying to circumvent the parasitic capacity, but they only affect the response (slow zero as opposed to a notch), because the current as seen from the bridge is still there, which is what is the problem.

My question(s): is there any way of making V(mid) fall with the end of the command pulse, actually having a dead-time in there? Another winding with a forced current, maybe? Some clever snubbers? Anything? Or is this "unobtainium"?

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Update: This is a close-up with Id(M3):

The dead-time is 25n but the rise time is imposed to be 25n, too. Tfall=1n but, apparently it doesn't affect the response as I'd want. Increasing the dead-time to 50n (keeping tr) results in this:

Answer 1

Just because M1 turns off (and M3 isn't on yet) doesn't mean that v(Mid) will go low -- what happens depends on the load current (and load inductance).

However in your circuit, that's not what is causing the shoot through current -- notice that in your 2nd waveform, V(gh,mid) rises slightly at around 6.05 us. This is because V(mid) is falling (by M3 turning on), but M1 (which was off) turns back on again. M1 turns of because of drain-gate capacitance which couples the increasing VDS of M1 to the gate of M1.

You can improve this by reducing the value of the 12 ohm, and/or slowing down the turn on of M3. Basically in these situations you need to ensure the turn-off 'strength' is stronger than the turn-on capability.

In more technical terms -- when turning on M3, the dV/dt of v(mid) is limited by the Miller capacitance CDG of M3 to dV/dt = I_gate/Cdg. However, similarly the gate current induced in M1 is also I = Cdg*dV/dt, which is a similar amount. To avoid M1 turning on, you need to have a higher magnitude of gate turn-off current than turn-on current.