I just wrote down a calculator core with VHDL which actually does a multiplication, additon, an Xor operation and an AND operation and I have to write a test bench which should simulate all four functions for all possible combinations of the two 8 bit operands. How could I write down a similar test bench since I have a button to increment the operands and the opcode value and one to select the operation and a last one a reset button. When I tried a test bench for only one case for each operation it was so long I think that there is another way to do it to test all the operand.
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\$\begingroup\$ Why not loop across the parameters and then in the center of the loop, assign the loop indices to the signals that drive the design. OTOH, if you want some real fun, you could use OSVVM's intelligent coverage. See the examples in the CoveragePkg_user_guide.pdf at osvvm.org. \$\endgroup\$– Jim LewisCommented Jan 19, 2016 at 17:20
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Its a bit unclear what your opcode is supposed to be, do you mean operands? What for do you need opcodes? Did you build some kind of cpu?
I would suggest to test all calculation modules on their own, especially for overflow and underflow (not for the mentioned operations) . Then I would also test your input module on its own and afterwards all modules together to make sure the bus system works correctly.
The reason is, that by doing it this way you can test a lot more thorough, because if you would simulate the whole system at once (so input together with the calculation modules) its takes a lot longer. You can therefor check a lot more different calculations in the same time when you test all modules seperatly.
If you want to get more specific input, you might want to add a schema how your system is set up.
