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I am working on a project which requires me to convert Mealy and Moore Machines into Flip Flops. Although the task isn't difficult, but it is exceptionally boring to repeat certain set of instructions, this makes it time consuming as well.

Is there an online/offline tool to automatically generate flip flop diagrams/Input Equations from a Finite State Machine?

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2 Answers 2

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Of course, that is what Hardware Description Languages (HDLs) are for. To describe Hardware, including state-machines, using close to natural language. Namely, VHDL and Verilog.

Some VHDL and Verilog editors will even generate graphic diagrams of your state machine from the code

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  • \$\begingroup\$ Would I have to write code to make FSM or there is a GUI? \$\endgroup\$
    – Tom Floyd
    Commented Apr 5, 2016 at 17:44
  • \$\begingroup\$ There are graphic tools for SM. Personally I prefer to code them in VHDL, so I have no experience with them. \$\endgroup\$
    – Claudio Avi Chami
    Commented Apr 5, 2016 at 17:47
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What you are looking for is a 'synthesis tool'. For example Design Compiler. These take a description of the logic (verilog, VHDL) along with timing/area/power, etc constraints and create the circuit implemented with gates from a library.

But the licenses are quite expensive so I doubt it would be worth it for a class project :P

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    \$\begingroup\$ Altera and Xilinx, among other FPGA manufacturers, provide free synthesis tools and you can get an RTL diagram of the HDL code you wrote. For free. \$\endgroup\$
    – Claudio Avi Chami
    Commented Apr 5, 2016 at 17:50
  • \$\begingroup\$ There you go, I forgot about the FPGA manufacturers. However, if you ever plan to interview I would just do the stable-table -> gate-level implementation by hand. Even though you know how to do them now, the repetition will help it stick in an interview 5 years down the road. \$\endgroup\$
    – jbord39
    Commented Apr 5, 2016 at 17:52
  • \$\begingroup\$ Good for you, but that is what you want, not what the owner of this question asked. \$\endgroup\$
    – Claudio Avi Chami
    Commented Apr 5, 2016 at 17:54
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    \$\begingroup\$ What are you some sort of stackexchange crusader? I provided an answer to the question which was the type of tool that does this work for him (synthesis tool). Then I gave extra advice, because honestly learning how to use some FPGA synthesis tool for a one-of synthesis experiment is going to take longer than just doing it by hand. And will actually give the user some knowledge that will last. You could also use ABC - this is built around the espresso algorithm for boolean reduction, and is completely free. eecs.berkeley.edu/~alanmi/abc/abc.htm \$\endgroup\$
    – jbord39
    Commented Apr 5, 2016 at 18:47

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