For few days I've been wondering why an std_logic_vector type can't get an unsigned/signed type.

My question is : does this constraint only comes from VHDL syntax and though this is implicitly needed by the compiler or does it have a real impact after synthesis and if so, how?

In other terms I'd like to know what are the effects of this :

signal my_slv_signal : std_logic_vector(7 downto 0);
signal my_unsigned_signal : unsigned(7 downto 0);

my_slv_signal <= std_logic_vector(my_unsigned_signal);
  • \$\begingroup\$ Look here \$\endgroup\$
    – Eugene Sh.
    May 18, 2016 at 14:53
  • \$\begingroup\$ Thanks for your answer but I'm not looking for information about the to_unsigned/to_signed or to_stdlogicvector functions of the numeric_std library. I know those functions return "std_logic_vector(input)" (or unsigned(...) / signed(...)). I'd like to know what those last conversions (without the "to_") are actually doing. \$\endgroup\$
    – A. Kieffer
    May 18, 2016 at 15:04
  • 2
    \$\begingroup\$ Or here : stackoverflow.com/questions/27403835/… \$\endgroup\$
    – user16324
    May 18, 2016 at 15:06


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