What does PLL order represent? What are the disadvantages in order 1 & 2 PLL comprared to order 3? How to choose the pll type for an application like QPSK demodulator?
It seems to me the accepted answer (by Sparky256) views the PLL simply as a filter and completely ignores its actual purpose, which is being a control system, controlling the phase of a signal. The order of a control system signifies its number of internal states. In a system that has a single input, the states beyond the first state (order) are equivalent to derivatives of the controlled variable.
Specifically, in a PLL, the controlled variable is normally the phase of the signal. The PLL attempts to produce a phase lock. So, the first order is for the phase variable/state, the second state is a derivative of the first state - which is frequency, and so on.
For a simple frequency synthesizer a first order PLL might suffice, but with a QPSK demodulator a first order PLL would probably be lacking as any carrier frequency offset between the modulator and the demodulator will always produce a constant phase lag, which can only be removed by a second order PLL. A phase lag means the I and Q channels cannot be fixed (they constantly "move"). Therefore, a QPSK demodulator should have a PLL with at least 2 states (i.e. 2nd order or higher).
Also, contrary to some notion prevalent in comments and answers here, a higher order doesn't make a system slower, nor does it make it faster. Response time is determined by all of the system parameters, mainly by the value of its coefficients (or the position of its poles and zeros, in filter design jargon).
I found this link to an amazing document that spells out the fine details up to 4th order filters.
Filter order just refers to the number of poles used to filter the output of the phase comparator so it provides a smooth DC error voltage to the VCO.
1st order filters are actually just the VCO's filter characteristics, requiring a minimum amount of time to settle down (zero phase) to a change in frequency or phase tracking. The raw phase comparator output voltage is fed to the VCO (voltage controlled oscillator) with only the noise spikes filtered out. This type offers fast tracking of frequency changes and locks quickly to the newest setting, but can have erratic output until it locks onto a new frequency.
A 2nd order filter has 1 RC stage, either passive or using an op-amp for a sharper roll-off. It is a tiny bit slower in locking onto a new frequency (zero phase) but less erratic in settling down and being stable. Recommended for most all PLL designs.
A 3rd order filter uses an optional op-amp and double RC networks. It settles down slower than the others but tolerates FSK/QFSK/QPSK better by staying stable even with complex modulation schemes. The RC networks have to be tuned for a given range of baud rates so a actual change in bit rate is followed as quickly as possible.
The PLL loop must always be able to find and lock onto a new carrier frequency rather quickly or loss of data occurs, forcing a resending of data packets or sending a EOF/EOL/EOT command first. Fortunately fast MPU's can emulate or have the entire PLL function blocks built in, so the use of analog filters and discrete PLL circuits are rare. Use QPSK as a search term and you will find plenty of support IC's and ready-to-use modules. Be careful of any 'special' software or license agreements.
These answers are obfuscated by theoretical terms and implementation details. The original question of selecting a PLL to demodulate a phase modulation scheme such as QPSK is ultimately not addressed.
Demodulation has no dependence on the order of the PLL.
Briefly though, let's cover the orders.
First order PLLs have limited lock band width. If a PLL is centered at a frequency \$x\$. Then it can track sine waves with frequencies of \$x \pm \Delta x\$. However, as the \$\Delta x\$ grows, it will be unable to track the signal. It's VCO output will have a small phase error (offset) relative to the original input signal if the input signal is a different frequency, and the offset will get worse as the frequency difference between the input and its center frequencies gets worse - until the difference is so great that it can no longer track the input.
Second order PLLs, because it has what is called an integrator, eliminate the phase error problem.
End of discussion about PLL order.
Demodulating QPSK or BPSK with a PLL depends on your error detector. For simplicity, lets discuss BPSK in the following:
To demodulate a BPSK signal using a PLL, we modify the error detector of the PLL so that the loop VCO locks to either 0 or 180 degrees with respect to the input signal. Thus, the output of the PLL VCO is either in phase or 180 degrees out of phase with the input. As far as the loop is concerned, because of the modified error detector, it thinks it has zero error.
When the input switches phase, the loop should do nothing, again, because the loop will lock onto either 0 or 180 degrees. However, some of the signals within the loop will change from positive to negative and you can use this change to detect if the signal switched phase.
The same concept extends to QPSK, where the PLL is blind to detecting phase changes of 90, 180, and 270 degrees in the input signal.
A PLL that can demodulate BPSK is called a Costas Loop.
I wrote this paper on how to implement a Costas loop in software, which contains all of the information I mentioned here in depth.
FakeMoustache wrote: "They all have zero phase difference in locked state"
Our terminology may differ but my understanding is that, in a first order design, the phase difference is used as the error signal (with amplification) and drives the VCO hence the phase error in lock depends on the frequency. A second order design integrates the phase difference to get the VCO control voltage hence the phase error is zero when locked to a fixed frequency and generally depends on the rate of change of the frequency being tracked for a slowly varying signal. For a third order design, the error would depend on the second derivative and so on.
Sorry for my english. In my opinion, the order of the loop filter depends for the performances that you want obtain. Generally low order have fast lock but bad performance with respect spurious attenuation; in addition using an higher order loop filter also an optimum shape of the Phase Noise can be recognize. Usually an analog PLL, the main spurious are rapresented by the unwanted signal due to the reference signal. This signal can be easilly clean using a simple filter (for example second order). In the digital PLL (for example the PLL that have Charge Pump) the unwanted signal have lower frequencies (ex.: fref/[2 or 3...] ). To obtain a clean output spectrum can be necessary use an higher order loop filter (3° or 4° order); in same cases it is possible also reduce the loop bandwidth. This way increase the time necessary to the lock. The main main concept in the PLL is "trade-off" :)