I am designing a low power phase locked loop in cadence with a phase detector, charge pump and VCO.The control voltage output for my circuit at the output of charge pump is as shown below
But when I zoomed into the waveform I saw some oscillations like this
Does this mean that my PLL is not locking properly because I thought, the control voltage must be constant when locked. But, here it is varying for 0.1Vpp. So how should I interpret my result? Is it right or wrong? Please, any help is appreciated.