SDRAM timing confusion

Question

I'm looking at this data sheet: T67M-512Mb-Mobile-Lpddr-Sdram (targeting speed grade -75) and trying to understand the timing requirements for performing a read, specifically when to sample the DQ input data lines. It gives a formula on page 27 for Data valid output window (DVW) being tQH - tDQSQ

Writing down the min and max values as <min,max> in unit of nanoseconds, I find tDQSQ on page 26 as <-,0.6> . I assume if the minimum is not stated, the worst case is 0?

A formula is given for tQH on page 27 as tHP-tQHS. tQHS is on page 27 and given as <-,0.75> while yet another formula is given for tHP as tCH,tCL. Not sure what a comma means here.

tCH and tCL are both found on page 26 with values of <0.45,0.55>

Plugging in all my values, I get a final formula of:

(<0.45, 0.55> - <0.0, 0.75>) - <0.0, 0.6>

This formula confuses me as there are values within the ranges that can result in an overall valid window time of zero, or even a negative value.

Am I calculating/interpreting this correct? Do these values means that there are no gaurantees that the output data will be valid?

Answer 1

After more research, it looks like the values could be negative. Relative to the clock, the data valid window can slide all around. To overcome this interfacing difficulty, the part includes a "data strobe" which has matched latencies with the data. Relative to this data strobe, the valid window has a much more consistent and reliable timing. Interfacing with this part would most likely require using the data strobe the clock in the data into the receiving registers.