So, I am trying to build an 8 bit multiplier in verilog. I am using an add/shift method to do it that uses a register. Whenever I run the code, it produces a result that isn't right. My verilog is:
`timescale 1ns / 1ps
module Mul8bit(
input [7:0] Multiplier,
input [7:0] Multiplicand,
input Clock,
output [15:0] led
);
reg M;
reg [16:0] ACC = 0;
reg start=1;
reg state = 0;
reg [15:0] led;
always @(posedge Clock)
begin
led <= ACC[15:0];
end
always @(posedge Clock)
begin
M = ACC[0];
case (state)
0:
if(start)
begin
begin
state = 1;
ACC[7:0]<=Multiplier[7:0];
end
end
1,3,5,7,9,11,13,15:
begin
if(M)
begin
ACC[16:8] <= ACC[15:8] + Multiplicand[7:0]; // Add
state <= (state+1); // increase the state
end
else
begin
ACC <= (ACC) >> 1;
state <= (state+2);
end
end
2,4,6,8,10,12,14,16:
begin
ACC <= (ACC) >> 1;
state <= (state+1);
end
17:
begin
led <= ACC[15:0];
start <= ~start;
state <= 0;
end
endcase
Additionally, this is my testbench:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/16/2016 08:12:51 PM
// Design Name:
// Module Name: 8bitMultiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mul8bit_tb(
);
reg [7:0] Multiplier = 8'b10101010;
reg [7:0] Multiplicand = 8'b00001111;
reg Clock = 1'b0;
wire [15:0] led;
Mul8bit Multi(Multiplier, Multiplicand, Clock, led);
initial
begin
end
always
#5
Clock = ~Clock;
endmodule
So, regardless of whehter the clock keeps going, the program should stop once it enters state 17. However, it continues going and the output is:
Is there any clear reason the program doesn't stop once it gets to state 17?
