sample input signals and check their values VHDL

I have 2 input signals - ID_1,ID_2 which sampled into id_vec.
LEDx_GRNn are output. In this point, only one of a,b,c,d should be '1' and the others '0', which after should make only one led on and the others off.

For some reason all the leds are on so I'm guessing I do something wrong.
Waht am I missing?
ID_1,ID_2 have the constants values.

signal id_vec :std_logic_vector (1 downto 0);
signal flag :std_logic;
signal a:std_logic;
signal b:std_logic;
signal c:std_logic;
signal d :std_logic;

id_vec(0)<=ID_1;
id_vec(1)<=ID_2;

a <='1' when id_vec<="10" else '0';
b <='1' when id_vec<="00" else '0';
c <='1' when id_vec<="01" else '0';
d <='1' when id_vec<="11" else '0';

LED1_GRNn <=  not (a);
LED2_GRNn <=  not (b);
LED3_GRNn <=  not (c);
LED4_GRNn <=  not (d);


It must be = and not <=

a <='1' when id_vec ="10" else '0'; b <='1' when id_vec ="00" else '0'; c <='1' when id_vec ="01" else '0'; d <='1' when id_vec ="11" else '0';

You want to compare if id is equal to 0 or 1 or 2 or 3. Not assign right?

After EDIT

<= also means LESS_THAN_EQUAL comparison which you don't want it to be for your case.

• <= is potentially valid (depending on the libraries used) because it's an inequality operator. But it might not do what you want! As an inequality operator it can never be mistaken for assignment, because assignment is not an operator, so the two uses of the symbol always appear in different contexts.
– user16324
Commented Dec 4, 2016 at 12:56