2
\$\begingroup\$

What is the difference between these statements in VHDL:

  1. if (clk'event and clk='1') then
  2. if rising_edge(clk) then

Are they equivalent ? Do you produce the same behavior (outputs) ? Why would one be used versus the other ?

Also is one synthesizable versus the other ? Which is better for synthesis correct coding ?

\$\endgroup\$
1

1 Answer 1

Reset to default
3
\$\begingroup\$

No, they are not exactly equivalent. The first variation

if (clk'event and clk='1') then

only works correctly if the previous state of the clock was in fact '0'. This works fine in most cases, but won't catch unusual cases, such as when the previous state was 'U', 'W', 'X' or 'Z'.

The second variation uses rising_edge()1, which specifically checks whether the previous state was '0' or 'L' and the new state is '1' or 'H'.

1 You can see the actual definition on Stack Overflow

\$\endgroup\$
4
  • 1
    \$\begingroup\$ So would it be correct to say it might be better to use rising edge to catch all possible cases if you are using U W X Z states ? \$\endgroup\$
    – user4434
    Commented Oct 13, 2020 at 18:41
  • \$\begingroup\$ @sheeple: Yes, that was the recommendation of my teacher when I learned VHDL 10 years ago. There still seems to be old VHDL code and ways of working on the internet. \$\endgroup\$
    – chthon
    Commented Oct 13, 2020 at 19:21
  • \$\begingroup\$ Okay, because many texts still use the if (clk'event and clk='1') then variation. Which is better for synthesis ? \$\endgroup\$
    – user4434
    Commented Oct 13, 2020 at 19:57
  • \$\begingroup\$ rising_edge and falling_edge. Because they require a change from an effective '0' and effective '1' behavioral simulation will match synthesis models. \$\endgroup\$
    – user8352
    Commented Oct 14, 2020 at 0:38

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.