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I wonder if the Altera DE1 and DE2 have the same UART? I got access to both the DE1 and the DE2 and I see a similar question but the manual isn't specific which FPGA is applicable.

UART core Altera De2

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    \$\begingroup\$ What are the components? You don't expect anyone to lookup, do you? Probably the core supports all range of Cyclone FPGAs. \$\endgroup\$ – Gregory Kornblum Feb 28 '17 at 11:42
  • \$\begingroup\$ @GregoryKornblum I apologize for the inconvenience. I'm a hardware noob and I don't even know what we mean when we say components. I'm basically trying to understand how I can learn the specifics and memory mappings of an UART and hopefully also use it. My task is to model an UART and eventually perform model-checking. \$\endgroup\$ – Niklas R. Feb 28 '17 at 11:54
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    \$\begingroup\$ Components- specific FPGA used on DE board. If you are writing your own UART, it definitely will not matter for which FPGA you are doing it. So memory mapping is whatever you will decide. Yet note, that the term "memory mapping" usually means that you have some CPU core or other mechanism with address space and memory, while in FPGA this is not mandatory. \$\endgroup\$ – Gregory Kornblum Feb 28 '17 at 13:12
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When talking about FPGAs we need to distiguish between "hard cores" and "soft cores".

A "hard" core is a section of the chip dedicated to a particular function. Your design just tells the synthisis tool how to hook it up.

A "soft" core is a core implemented in FPGA logic, it may be supplied by the FPGA vendor, it may be bought from a third party, it may be freely downloaded from somewhere like opencores, it may be written by yourself. Some "soft" cores may be written in generic verilog, others may be specific to a device familily.

I have never seen a FPGA with a hard UART. SO you are going to have to use some kind of soft implementation.

The DE1 and DE2 use the same FPGA family so it shuld be possible to use the same UART cores on both of them.

The problem I have found with alteras cores is they assume you are using altera's avalon bus system. I have found it's often easier to write serial transmit/receive code from scrath than to figure out how to glue the rest of my design to an inappropriate bus system.

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  • \$\begingroup\$ I think Lattice have FPGAs with hard UARTs. Although they are so hard to use that no one does :) \$\endgroup\$ – Gregory Kornblum Feb 28 '17 at 13:13
  • \$\begingroup\$ And I guess some of the FPGA SoCs probablly have UARTs on the processor side. \$\endgroup\$ – Peter Green Feb 28 '17 at 14:58
  • \$\begingroup\$ Zynq has. But it's a very different story. \$\endgroup\$ – Gregory Kornblum Feb 28 '17 at 17:09

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