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In the Atmel SAME70-XPLD board, there is a 2MB (2 bank x 2K row x 256 col x 16 bit) SDRAM (ISSI IS42S16100F-5BL). It is connected as follows:

SAME70-XPLD SDRAM

I don't understand why the A0 pin of the SDRAM is connected to ADDRESS2 of the MCU. Since this is a 16-bit wide memory, shouldn't this be ADDRESS1 so that each address is 16-bit aligned?

The schematics for the board can be found here (page 48 is the SDRAM): SAME70-XPLD User Guide

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It seems from their schematic and table 4-17 from your provided link that Address 0 of the MCU is used to control the bank selection from the memory. So that's why the address pins of the MCU are offset as you noticed.

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  • \$\begingroup\$ A0 is used for the LBE byte lane select, no? \$\endgroup\$
    – M D
    Commented Apr 17, 2017 at 17:26
  • \$\begingroup\$ Yes, you are correct but still more or less the Address 0 line is used for an alternate function already, in this case a control signal, therefore making it unavailable as address 0 and therefore you have the offset in the address line \$\endgroup\$
    – Kvegaoro
    Commented Apr 17, 2017 at 17:45
  • \$\begingroup\$ Agreed, but then I would expect A1 to be connected to the SDRAM's A0 pin. They show it as A2 which is 32-bit aligned, right? \$\endgroup\$
    – M D
    Commented Apr 17, 2017 at 17:51
  • \$\begingroup\$ Not because since A0 on the MCU its not available connecting A2 from the MCU to A0 in the SDRAM would leave as 16-bit aligned since A0 in the MCU doesnt really count towards addressing anymore since it is a control line \$\endgroup\$
    – Kvegaoro
    Commented Apr 17, 2017 at 18:23
  • \$\begingroup\$ In other words A0 isnt running as address zero, it is running NBS0 which is the proper control line for LDQM, therefore in this instance addressing lines start at A1. \$\endgroup\$
    – Kvegaoro
    Commented Apr 17, 2017 at 18:25

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