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Please check the schematic here> http://i.stack.imgur.com/opImI.png

Here is the circuit that I have developed. I am not very sure about the design.

Here is what I want it to do. When the user presses the push button S2 the TPS_EN line should toggle.

I am using BSS84 P-ch mosfets.The resistor values are as in the schematic.

Here is an explanation of how the thing should work.The TPS_EN line is low at first. Since it is pulled down by a 10k pull down resistor(not shown in the schematic).When the user presses S2, the mosfet Q2 turns on because ground is applied to its gate. which enables the power regulator connected to the TPS_EN line . The regulator now starts up and starts powering the microcontroller. The microcontroller pulls the LATCH_OP1 and LATCH_OP2 low. The mosfet Q2 and Q6 now 'turns on' due to this.Q6 is turned on and now causes the 1st and 2nd terminals of the push button s2 to go high. And the LATCH_OP1 causes the Q2 to latch thus enabling a constant high signal (VBATT)on the enable line.

Now when the user presses the button Since Q6 was 'on' the VBATT gets applied to gate of Q2 and turns off Q2.The regulator turns off. turning off the microcontroller and the LATCH_OP2 and LATCH_OP1 return to VBATT.

BATT is around 3.7v.The Micrcontroller is running on a 3.3v supply

The circuit does not work as intended. I tried manually changing the latch lines to ground when turning on and it worked. But when i connect the lines to the microcontroller it does not work Please help me out!

Feel Free to point out mistakes if any. This is my First circuit design!(So please excuse my noobness! :p)

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  • \$\begingroup\$ I don't understand: the point is to turn on and off the uC pushing the button? \$\endgroup\$ – clabacchio Apr 21 '12 at 9:23
  • \$\begingroup\$ yes. Once the button is pressed the microcontroller will latch the state to turn the system on(and to maintain it in that state). now when the button is pressed again the microcontroller will turn off releasing the latch and hence the entire system (including the microcontroller)will turn off. \$\endgroup\$ – user7994 Apr 21 '12 at 9:43
  • \$\begingroup\$ Are you using a LDO to power the micro? But this is OT...What's the microcontroller? Have you checked the datasheet about how to power it on and off? \$\endgroup\$ – clabacchio Apr 21 '12 at 9:46
  • \$\begingroup\$ could you add a state transition diagram of your required specification. \$\endgroup\$ – Standard Sandun Apr 21 '12 at 10:09
  • \$\begingroup\$ I could assume when it's on, the LATCH_OP1 is low. So that's why it won't change it's status. Add a 10K resistor in series of LATCH_OP1 line. \$\endgroup\$ – Standard Sandun Apr 21 '12 at 10:11
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I haven't examined the circuit much yet, but one thing you'll have to be wary of is switch bounce. If you were to look at the voltage at the switch, instead of seeing a nice perfect square wave as you might imagine, what you'd actually will horrify you.

Switch bounce

This is a real effect and happens on almost all switches. Assuming your circuit works, switch bounce will totally mess things up, because it will cause TPS_EN to toggle multiple times with every press of the switch.

What you need to add is known as a debounce circuit:

Debounce circuit


Having said all that, I think there's a better way to solve your problem, using fewer components.

You already have a microcontroller, so let that do all the hard work.

MCU Power

When you press S1, it causes Q1 to switch on, which powers the MCU. Immediately, the MCU raises the MCU_Signal line, which keeps Q1 switched on, even if you let go of the button.

From now on, the MCU keeps a watch on the Switch_Detect line. It will go high when the switch is pressed again. The MCU waits for the button to be released, then waits a further 100ms. This is to make sure the switch has really finished bouncing. Then the MCU lowers the MCU_Signal line, causing it to power off.


Added:

There's also the LTC2955 Pushbutton On/Off Controller which does the same thing.

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  • \$\begingroup\$ If Q1 is NMOS (as you drew it), the MCU will not receive VCC volts, but instead {Vg-Vgs_th}=approx={VCC-0.7-Vgs_th}. It is better to use a PMOS there (and, of course, excite it in a different way). \$\endgroup\$ – Telaclavo Apr 21 '12 at 12:13
  • \$\begingroup\$ @Telaclavo - I figured there'd probably be a problem with the FET. I'm not good with FETs. \$\endgroup\$ – Rocketmagnet Apr 21 '12 at 13:01
  • \$\begingroup\$ @user7994 - I've just realised that you're using an LDO with enable input. You may be able to get rid of the FET and use the enable input instead. \$\endgroup\$ – Rocketmagnet Apr 21 '12 at 13:02
  • \$\begingroup\$ yeah that's a good suggestion. Here's the circuit i plan to implement. postimage.org/image/icpsnngcj \$\endgroup\$ – user7994 Apr 23 '12 at 10:48
  • \$\begingroup\$ When the switch Is pressed the regulator enable goes high.The diode fwd drop is around 400mV (bat15-03w diode)and i can afford a max of 700mv drop to 'enable' the regulator.the system turns on and the microcontroller then latches the enable pin to high. the diode used in both places is the same. R7 and R11 are pull down resistors. Let me know if there are any potential drawbacks of this circuit. and also any suggestions for a low drop schottky diode for d1 and d4 will be appreciated!Thanks a lot all for helping me out :) \$\endgroup\$ – user7994 Apr 23 '12 at 10:54
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Just to point out a few things that were wrong in your schematic:

  • You have Q6 upside down. The way you have it, there would always be current flowing through its parasitic diode, and through R25. So, Q6 is always "on", no matter what you do to its gate.
  • When LATCH_OP1 is low (pulled low by your MCU), pushing S2 would create a low-impedance path {VBATT --> parasitic diode of Q6 --> S2 --> NMOS of your MCU output}. The high current created could damage Q6 or your MCU.
  • "turning off the microcontroller and the LATCH_OP2 and LATCH_OP1 return to VBATT". No. When you turn off the MCU, its outputs don't go to VBATT. This depends on the specific GPIO implementation but, in most cases, all GPIO pins will stay connected with two diodes to GND and VDD. One diode goes anode to cathode from GND to the GPIO pin, and the other diodes goes anode to cathode from the GPIO pin to VDD. So your GPIO pin can never be 0.7 V below GND or 0.7 V above VDD. VDD will be zero (or close to it, if you inject a significant current through the upper diode of any of the GPIO pins). In any case, the GPIO voltage won't be VBATT. Probably, it will be so low that it will keep the gate of Q2 low, and Q2 on (thus, turning on again the regulator).
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You designed an elgantly simple T flip flop concept. suggestions to avoid:

(1) avoid interface with uC to prevent latchup SCR effect of CMOS uC when voltage applied to any signal pin when Vdd is off.

(2) avoid design that drains Vbat when switch is not used

(3) need switch debounce cap. preferably across switch to burn contact oxidation. Reliable low current switches are gold plated. ($)

{1} Consider logic T type Flip Flop for your solution

{2} Consider D type Flip Flop with -Q connected to D (=T FF) and use Clock input to switch and -Q to TPS_EN.

{3} "In your design spec !!" Specify if you want action on switch make or break" but consider Clock input prefers fast rising input to avoid internal race condition if any.

{4} Switch bounce can discharge cap in 1 bounce but with long bounce time (0.5~5ms) determine bounce time and make RC time 10x for margin.

Cost is ~0.12 for D FF (1 of) http://search.digikey.com/us/en/products/SN74LVC1G80DCKR/296-9852-1-ND/380101 for example

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