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Could someone explain the most important reasons for an analog designer to use MOSFET transistors in the subthreshold regime? What are the advantages and disadvantages? Generally, the circuits in mind that use transistors in their subthreshold regime should have 1) low noise 2) low power and 3) should amplify signals!!!

Note: I know that in the subthreshold regime, gm takes the maximum value for a constant bias current.

For example, in below circuit, why should we use the transistors in the subthreshold regime if we are biasing the circuit with Ibias? Why would the power consumption of this circuit be smaller if the transistors are operating in the subthreshold region? In this circuit, we have constant power supply (VDD and VSS) and constant biasing current (Ibias).

enter image description here

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  • \$\begingroup\$ If the circuit adjusts its current, to achieve a certain speed (e.g. 10nanosecond logic delays), then power is greatly reduced and battery life become enormous. \$\endgroup\$ – analogsystemsrf Jun 13 '17 at 14:38
  • \$\begingroup\$ analogsystemsrf thanks for your response.But this is a analog circuit and we don't care for the speed but for noise, gain, power consumption \$\endgroup\$ – elecV1 Jun 14 '17 at 8:27
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The subthreshold region is used for low-voltage / low-power applications that might be powered e.g. by energy harvesting, where supply voltages have to be as low as possible to avoid additional losses in DC/DC converters.

As for disadvantages, according to Reynders, "Sub-Threshold Operation: Theory and Challenges" (2015), which dedicates a whole chapter to the topic, challenges are

  • Performace (increased propagation delay for digital circuits),
  • Leakage (which plays a bigger role compared to higher supply voltages), and
  • Variability (increased effect of device to device variations due to the exponential current/voltage dependency)

See this document for extensive information on the topic. For applications, entering "subthreshold low power" into your favorite search engine leads to lots of topics, ranging from microcontrollers to biomedical systems. There are also other books on the topic.

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  • \$\begingroup\$ Thank you very much cx05.But if a circuit has constant DC power supply(e.g 1.8V ) and biasing with constant DC current (e.g 100uA) how why someone to use transistors in this region?The power consumption of the circuit regardless of the region in which the transistors will operate will be the same because we hace constant current and constant power supply.So P=V*I = ... \$\endgroup\$ – elecV1 Jun 13 '17 at 11:37
  • \$\begingroup\$ Take a look at the second part of @Joren Vaes answer for analog applications. \$\endgroup\$ – cx05 Jun 13 '17 at 11:42
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    \$\begingroup\$ @elecV1 The gm at a certain current draw is different. If you don't need/expect large swings and can deal with large distortion, you can get more current gain (dIout/dVin) for a given bias current. It's also important to understand that the operating region is determined at the design time of the device. For a given current the circuit could potentially achieve more small signal gain. Generally, people also design for a certain gain, trying to keep the power low. A circuit with a WI biased input stage might have less current needed for a certain achieved gain. \$\endgroup\$ – Joren Vaes Jun 14 '17 at 6:48
  • \$\begingroup\$ Joren Vaes so if I understand correct your thoughts the gain in subthreshold regime will increase because the gm will be increased.But sometimes the gain not only depends by the gm but also by the output impedance.Also in subthreshold regime the total current in the circuit will not decrease but its benefit to use transistors in subthreshold regime because with the same bias current we can achieve highest gain. \$\endgroup\$ – elecV1 Jun 14 '17 at 8:18
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The region below threshold has generally just been a footnote; however, subthreshold operation has several desirable characteristics, such as simple physics, high-transconductance, and “sharp-edge” transitions in digital applications. In contrast, the temperature dependence of diffusion movement due to the thermal voltage terms is substantially greater than with super-threshold designs that operate through drift movement. In analog applications, subthreshold gives you high gain, and in digital applications, it can give you lower power.

A good reference for this that is not paywalled is Jen Hasler's Neuromorphic Roadmap.

Subthreshold has the highest gate for an operational region; however, it generally breaks the classical concepts of what people are comfortable deal with. You can easily see this if you start with the math, and to unify operation, use the EKV model:

$$I_{nFET}=I_{f,r} =\frac{W}{L}2 U_{T}^2\frac{\mu C_{ox}}{ \kappa}\ln^2 \left[1 + e^{\left({\kappa\left(V_g-V_{T0}\right) - V_{s,d}}\right)/\left({2 U_{T}}\right)} \right]$$

The mathematical form of \$ln^2 \left(1 + e^{\frac{x}{2}}\right)\$ between the regions of operation let's you take a Taylor Expansion around the point of operation. For your pFET, the equation is

$$I_{pFET} =I_{f,r} =\frac{W}{L}2 U_{T}^2\frac{\mu_p C_{ox}}{\kappa}\ln^2 \left[1+ e^{\left[{\left(\kappa \left(V_b -V_g+V_{thp}\right)\right)- \left(V_{b}-V_{s,d}\right)}\right]/\left({2 U_{T}}\right)} \right]$$

In the analog sense, you are looking for a high \$g_m\$, and subthreshold gives you this. In your schematic, your diff-pair is basically a source follower, and you want to have the biased transistor in subthreshold for the maximum gain on the diff-pair. In above threshold, you'd basically have no gain and a terrible amplifier. Also, the power is lower because the flux is conserved through the circuit so your current mirrors will not use more current than is supplied to them, and that current is limited by your bias transistor.

Subthreshold is not bad to design with if you understand devices. I have found that most issues regarding analog in subthreshold can be addressed with symmetry and careful design.

In the digital sense, the digital designer is driven by the incentive of “faster” designs. The megahertz race of the nineties and naughties, and the constant need for speed driven by the desire for faster software, has resulted in designers rewarding complexity over simplicity. Transistor scaling has done an excellent job of giving similar, but not perfectly scaled, transistor changes with feature size. Regarding scaling, one often hears references to “Moore’s Law”, but the concept of scaling is generally not understood by those who casually throw around the term. This has manifested in "faster" CPUs that generally can do less per Watt.

powerwall

As the graph shows, the data suggests that scaling is steadily decreasing computational efficiency of digital processors. The larger question is whether this decreasing computational efficiency will trend toward an efficiency barrier asymptotically, or just have a decreased slope when compared to previous generations. There is basically a powerwall that exists if you use above threshold operation for digital devices. You can easily see this in I-V curves from a commercially available 14nm process:

enter image description here

The graph above show a linear plot, and you can see that the devices are not compliant to the "square law" due to higher order effects. However, the subthreshold regime is pretty nice:

enter image description here

The reason that you could consider subthreshold "slow" is that the current is lower and it takes longer to charge a gate capacitor of a fixed size; however, you have fewer higher order effects.

For the best power processing per-Watt, you can just design to run in subthreshold at near threshold. If you want to "double your speed" in standard designs, you basically have to double the power. I just take my digital designs and run them in asynchronous wrappers so that I can operate them at "near threshold" where the gain is still good and I don't lose a lot of power to the higher-order issues, such as "band-to-band" tunneling that we see a lot of on 24nm and smaller nodes.

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  • \$\begingroup\$ Thanks b degnan.You refer that "The reason that you could consider subthreshold "slow" is that the current is lower and it takes longer to charge a gate capacitor of a fixed size;"But in the circuit (for example in the picture which I had post) the bias current is constant, how the current decrease in subthreshold regime?I'm a little confused with this sentence you write above \$\endgroup\$ – elecV1 Jun 14 '17 at 8:23
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    \$\begingroup\$ @elecV1 The bias current sets the current of each leg in the circuit. Your circuit should already be in subvt to have high gain, so the issue is the slew on the output stage at Vout. If you change the bias from 10nA to 1nA you'll notice a significant increase in time due to the capacitor equation. \$\endgroup\$ – b degnan Jun 14 '17 at 13:44
  • \$\begingroup\$ Thanks b degnan.In this applications the speed of the circuit, it hasn't got an important role.The most important characteristics for this application, is the high gain and the low power consumption. \$\endgroup\$ – elecV1 Jun 17 '17 at 8:49
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There is the fact that the gain is highest for a given current in the subthreshold regime. This can be useful in low-power applications where you want to waste as little power as possible. Of course, the downside is that this will require large devices to get a certain amount of gain in the first place.

Another application is when we desire the exponential behaviour of the current vs gate voltage. This can be used for example in reference circuits such as bandgap references. However, there are downsides to this, and in a CMOS process, it is often desirable to use parasitic BJTs instead of weak-inversion FET devices.

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