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A couple of months ago I started working on developing my own computer to learn more about its low-level functionality, the design process and the architecture behind it. Although I look at real-world examples of other computers I try not to just copy, but use those as inspiration to develop the architecture of my computer myself.

Besides 555 CMOS timers, some EEPROMs and HM62256 SRAM everything else is supposed to be built discretely with 74 series ICs.

I planned it to have a 16 bit word length, but didn't think about the implications this would have for the RAM as opposed to all the 8 bit computer examples I've read about.

My first approach was to make the RAM word-addressable, so I hooked up the address lines of two HM62256s and effectively had 16 bits stored in every address. This would be easy to output to the bus and work with, so I developed an instruction set around it, with a 5 bit opcode and the remaining 11 bits depending on the type of the instruction left for registers or immediate values.

While doing more and more research however I realized that word-addressable RAM doesn't seem to be common in real world computers. They all seem to be addressable by byte. This wouldn't be a problem for 8-bit computers, but if I plan on fetching my instructions in just one cycle doing it this way would be a problem.

Especially looking at ASCII it seems important to have a way to store single bytes in RAM, not just whole words. If I were to store ASCII characters in 2-byte RAM addresses, there'd be 50% wasted storage. I could just ignore this and carry on with my plans, but I'm also really intrigued by how this is solved.

How am I able to fetch multiple bytes from a byte-addressable RAM simultaneously to use them in my instruction register? Would I have to read two bytes in sequence and re-assemble them into a single 16-bit instruction before storing it in the register? What about other kind of data, does reading a 2-byte value require me to load two bytes from RAM manually into registers and re-assemble them?
Is there a more useful (or simpler) way I just can't think of?

Sorry for the long read for that short question, but thanks for any replies.

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  • \$\begingroup\$ The 8086 (not 8088) added a bus high enable line. When \$BHA=0\$ and \$A_0=0\$ then the implied data bus was \$D_0-D_{15}\$; when \$BHA=0\$ and \$A_0=1\$ then the implied the data bus as \$D_8-D_{15}\$; when \$BHA=1\$ and \$A_0=0\$ then the implied data bus was \$D_0-D_{7}\$. The remaining bus cycle case was supposed to be ignored. \$\endgroup\$ – jonk Sep 11 '17 at 23:37
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    \$\begingroup\$ you treat word access as you do now but handle single byte and non-aligned words as special cases. Before that you need switch word-address to byte-address(by shifting the address bus up one bit on the momory side and wire the LSB on the memory side to 0). Currently most RISC-like ISAs choose to implement non-aligned word access and byte access as special instructions and let compiler opt-in, to reduce hardware complexity. \$\endgroup\$ – user3528438 Sep 11 '17 at 23:39
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    \$\begingroup\$ As others have said, you leave the RAM as word-addressable and then select which byte out of the word you want. \$\endgroup\$ – pjc50 Sep 12 '17 at 9:03
  • \$\begingroup\$ Since addresses for data are supposed to be reserved at the end of programs instructions should always be aligned and at most one byte of data at the end is unused, so unaligned word access really only makes sense in few cases. If I were to access bits 0..7 only, does it make sense to shift them over to be put on the bus at 8..15, or do I leave them essentially shifted to the left by 8 bits? \$\endgroup\$ – Padarom Sep 12 '17 at 9:11
  • \$\begingroup\$ And if I understand it correctly for unaligned word access I'd need to essentially address MAR+1 in the first chip and MAR in the second and put them on the bus in reverse order? \$\endgroup\$ – Padarom Sep 12 '17 at 9:15
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Most architectures that encounter this situation have two (or more) different instructions for accessing Bytes or Words. If you have a 16bit datapath (word size), that means the hardware outside the memory can accept/deliver 2 bytes in a single cycle. How the memory handles this is up to the memory. If you only have an 8-bit databus within the memory unit, then you will have to do one of the techniques you suggested (2 cycles, 2 register transfers, etc).

However, I've never seen that in modern hardware because it's silly when cost and technology do not practically require it. As a historical note:

The very first PC processor - the 8088 from intel - was a 16-bit processor with an 8-bit memory bus. And there were 386's [32-bit data bus] with 16-bit [external memory] bus (386SX). -- TurboJ

Now, almost all practical hardware has memory (L1) width = processor width. The instructions will simply pick what to do with the mapping. Load word instruction = 1:1. Load byte = 2:1 (usually there is a range of instructions that determine what to do with the other byte in the datapath that isn't being loaded from memory).

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  • \$\begingroup\$ The very first PC processor - the 8088 from intel - was a 16-bit processor with an 8-bit memory bus. And there were 386's with 16-bit bus (386SX). \$\endgroup\$ – Turbo J Sep 12 '17 at 3:21
  • \$\begingroup\$ @TurboJ -- Oh yeah! The good old days! I meant recently, let's include the historical note. \$\endgroup\$ – DrFriedParts Sep 12 '17 at 4:51

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