For an LVDS signal, I am trying to understand what will happen if the transmitter's positive and negative sides of the differential pair get swapped on their way to the receiver. In other words you have two output pins on a transmitter, LVDS_Positive and LVDS_Negative. A receiver has two pins, LVDS_+ and LVDS_-. The LVDS_Positive gets routed to LVDS_- and vice-verse.
My intuition tells me that for a standalone clock (perhaps a clock buffer or an LVDS mux with selectable clock inputs) this will work perfectly fine the same as if it were routed + to + and - to -. This is because the polarity only swaps which edge is rising and which is falling, the clock is still propagated to the chip just fine, that skew is irrelevant I would think (unless there's a specific application where you are trying to align clock edges to bring in data or something like that.)
However for a data signal, example shown below, this would NOT work because it does not switch polarity every period as a clock does (depending on what bits the data contains), so transmitted 1's would be received as 0's and vice versa so the data would be corrupted.
I also know that certain standards, like PCIE, have built in that they can accept polarity differences in differential data signals which confounds this further.
Any help to understand this would be appreciated.