Effect of swapping positive and negative traces in a LVDS differential pair, for both clock lines and data lines?

Question

For an LVDS signal, I am trying to understand what will happen if the transmitter's positive and negative sides of the differential pair get swapped on their way to the receiver. In other words you have two output pins on a transmitter, LVDS_Positive and LVDS_Negative. A receiver has two pins, LVDS_+ and LVDS_-. The LVDS_Positive gets routed to LVDS_- and vice-verse.

My intuition tells me that for a standalone clock (perhaps a clock buffer or an LVDS mux with selectable clock inputs) this will work perfectly fine the same as if it were routed + to + and - to -. This is because the polarity only swaps which edge is rising and which is falling, the clock is still propagated to the chip just fine, that skew is irrelevant I would think (unless there's a specific application where you are trying to align clock edges to bring in data or something like that.)

However for a data signal, example shown below, this would NOT work because it does not switch polarity every period as a clock does (depending on what bits the data contains), so transmitted 1's would be received as 0's and vice versa so the data would be corrupted.

I also know that certain standards, like PCIE, have built in that they can accept polarity differences in differential data signals which confounds this further.

Any help to understand this would be appreciated.

Answer 1

For clock signal, swapping positive(+) and negative(-) at the receiver inputs leads to 180 degree phase shift. Depending on the signal transmission lines delays it may lead to improper data sampling, you may fix this by changing active edge of the clock signal (if it is possible with the system you work on), the situation may be worse when double data rate is used.

For data signal you are right, '1' will be received as '0' and vice versa. Some SerDes'es, for example Xilinx GTY transceiver offers hardware mechanism for swapping bit values.

If RXP and RXN differential traces are accidentally swapped on the PCB, the differential data received by the GTY transceiver RX are reversed. The GTY transceiver RX allows inversion to be done on parallel bytes in the PCS after the SIPO to offset reversed polarity on differential pair. Polarity control function uses the RXPOLARITY input, which is driven High from the interconnect logic interface to invert the polarity.

Source: UltraScale Architecture GTY Transceivers User Guide UG578 (v1.3) page 238, September 20, 2017

Answer 2

It all depends on the your device hardware and protocol.

Most implementations will insist on the correct polarity. Note if you change polarity at both ends of the LVDS link, the final result is correct.

Some implementations have hardware that makes signal inversion trivial, but you have to select which you have.

Some implementations may handle polarity inversion automatically without user intervention.

You will have to RTFM for the standard + hardware you are using, to see whether you are allowed to be sloppy in your LVDS polarity management or not.