Before I asked the question, I've googled advantages of the one-hot state encoding compared to others such as binary and gray state encoding.

I could understand one-hot's advantages and disadvantages over others encoding scheme, such as constant hamming distance (two), fast but requiring an N flops, etc.

Many articles mentioned that the one-hot is fast and it suits high-speed design and they also mentioned the reason is that it has very small decoding time compared to gray coding and binary coding.

However, I couldn't understand why one-hot decoding is faster compared to others. For example, when we decode the one-hot encoded state machine, it could be implemented by the case statement like below

parameter STATE_ONE    = 3'b001,
          STATE_TWO    = 3'b010;
          STATE_THREE  = 3'b100;
parameter STATE_ONE_ID = 'd0,
          STATE_TWO_ID = 'd1;
          STATE_THR_ID = 'd2;
reg [2:0] states;

  states[STATE_ONE_ID]: begin end
  states[STATE_TWO_ID]: begin end 

Also for the binary encoded states we could use below code for decoding

parameter STATE_ONE   = 2'b00,
          STATE_TWO   = 2'b01,
          STATE_THREE = 2'b10;
case (current_state)
  STATE_ONE   : begin end
  STATE_TWO   : begin end
  STATE_THREE : begin end 

When we look at the RTL implementing the decoder for one-hot and binary, it looks not really different.

I would like to know why one-hot decoding is much faster than the binary case?

Is the difference induced when they are synthesized?


1 Answer 1


The thing to remember about Verilog behavioural code is that what may seem like "we could simply do", doesn't actually represent how simple or complex the resulting hardware is.

Your case statement is describing the behaviour that you want, but the synthesis tools have to convert it in to logic gates. There is no simple case logic gate. Both infer chains of multiplexers for each signal controlled within.

In the one-hot example, the logic checking the state can simply use the one-hot bits for the multiplexing.

For the binary-encoded state, the logic has to include a load of decoder logic to convert the binary value to a one-hot value before it can do the multiplexing.

TL;DR; The difference basically comes down to where the decoding logic is placed. In one-hot, the logic is placed before the state machine registers which breaks up combinational paths (good). In binary, the logic is placed after the state machine registers forming longer combinational paths (bad).

  • \$\begingroup\$ Thanks for a clear answer. The point is that the implemented hardware will use the MUX to decode the states and inputs to the MUX should be one-hot to select correct state. I have one more question. If we use the FPGA which utilizes the LUTs instead of the MUX, can we say that decoding in both schemes are almost same? Also I couldn't understand what do you mean by the logic is placed before the state machine registers which breaks up combinational paths (good). \$\endgroup\$
    – ruach
    Feb 3, 2018 at 12:27

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