I have designed boost converter with Peak current mode control in PLECS. I have used the method of k factor approach to design the compensator. the bode plot transfer function of the power stage is used to select the crossover frequency of 40KHz as I am using a switching frequency of 2.2MHz and from this, I defined my compensator which shows a good bode plot(enter image description here). the bode plot of the complete system is perfectly matching my expectation as you can see in the figure. however, when I run the same circuit in PLECS with the compensator I get a huge oscillation and non-stable system and the compensator(enter image description here) is meant to stabilize my system ( I could not upload the file in stackoverflow). my question how can the frequency domain analysis works perfectly but when it comes to time domain( circuit) the system is completely wrong? I have used a crossover frequency of 5KHz and shows the good result which means that my control loop does not show good behavior when it comes to higher crossover frequency which goes against my understanding that says I Can choose any crossover frequency as long as it is tenth less than the switching frequency. the bode plot of the compensated circuit(circuit with the compensator) is :enter image description here the circuit:enter image description here the cross over freqquency where it is unstable is 40KHz, I have chosen phase margin 60 and with the k factor approach I calculated the pole zeros and gain of the comensator

  • \$\begingroup\$ It's totally unclear from your bode plot what the compensated response is. Show the bode plot of only your compensated circuit. Also state what frequency the unstable system is oscillating at AND IMPORTANTLY show you circuit. \$\endgroup\$ – Andy aka May 22 '18 at 10:08
  • \$\begingroup\$ Hi Andy, i just edited it. I guess you mean the compensated circuit is the circuit with the compensator.thanks \$\endgroup\$ – Yaakov May 22 '18 at 10:33
  • \$\begingroup\$ For your bode plot where was your input and where was your output measured and how did you arrange the schematic so that the feedback was removed i.e. how did you measure the open-loop gain for your bode plot? \$\endgroup\$ – Andy aka May 22 '18 at 10:39
  • \$\begingroup\$ for the bode plot, the input is the Verr (Vref-Vout) to the voltage output Vout, I have used the goto/from signals(Vout and I_ind) instead of wires. I used Vout/Verr transfer function(mathematical transfer function given by Basso) and I used as well the analysis tools of PLECS to get the open loop (Vout/Verr) \$\endgroup\$ – Yaakov May 22 '18 at 10:49
  • \$\begingroup\$ The deal with the switching frequency is that it creates a peak in the response graph at 1/2 fsw so you want to have a good attenuation at that point. It's a bit simplistic to say 1/10th switching frequency for fco. You can try your PLECS model versus the one TI simulator provides, the latter is about as good as you can do without measurements. \$\endgroup\$ – Barleyman May 22 '18 at 11:45

Modelling current mode SMPS is in fact a fair bit harder than voltage mode, whatever the "everyone knows" knowledge says. It's often easier to USE and you have "known good" formulas but these tend to throw away the current amplifier part, or "simplifies" it away..

If you have two feedback loops in parallel, eliminating one and saying it doesn't matter is largely a hand-waving excercise. You can often get good enough approximation of the result and the manufactures often do not provide the necessary information to model the current mode loop. So it's not totally unreasonable to drop the current loop response because you don't have a reasonable way of modelling it anyway.

What I'd recommend is going over to Texas Instruments web page and trying their webench tool suite to design a similar power supply. If you use same/similar the same inductor/capacitor/transistor and a current mode controller, the feedback loop should be pretty close to what you do need. You probably need to change the voltage divider to provide the correct feedback value which does affect the loop somewhat but the webench lets you play with the feedback values on component level.

If you're interested in the complexities of properly modelling current mode SMPS controller, check "UNDERSTANDING AND APPLYING CURRENT-MODE CONTROL THEORY" by Robert Sheehan plus his other white papers. Other methods are presented in some textbooks such as "Switching Power Supply Design & Optimization" by Sanjay Maniktala. These all rely on the manufacturer actually disclosing waveform details and specs of the controller current mode amplifier which is often not given.

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  • \$\begingroup\$ I have tried very hard to model it for couples of weeks but did not accomplish it so I just use some models as you said, Now I come to the compensation design which is not obvious as it seems from the textbook I used (Pr.Ned Mohan) and I really don't like when the theoretical calculation( that looks correct ) is not in line with simulation circuit. I am going to look at the references you have given to me and thanks for the hint \$\endgroup\$ – Yaakov May 22 '18 at 11:21
  • \$\begingroup\$ @yaakov That's the problem with simulators, you cannot know if it's being simulated properly. Simulating a CMC SMPS in SPICE is tricky for the same reason as making a model for it is. At the end of the day you cannot beat measurements, but you need a vector analyzer to do it properly and this is an unreasonably expensive piece of kit, £1000+ usually. \$\endgroup\$ – Barleyman May 22 '18 at 11:41
  • \$\begingroup\$ that is why I wanted to use PLECS and Simulink as the first approach as they seem more straightforward but still, I am getting completely meaningless result and this before going to the measurement \$\endgroup\$ – Yaakov May 22 '18 at 12:13

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