Soft latching power switch

Question

I have stumbled upon a soft power switch with low part count on EEVBlog, which I found very interesting for my hobbyist projects: https://www.youtube.com/watch?v=Foc9R0dC2iI

Since it uses a PMOS and I only had a NMOS to try the circuit out, I have mirrored the whole circuit:

Initially there was no R5 but I found the circuit to be unstable (it sometimes switched to on without pushing the button), so I added R5.

The circuit works now, but the expected oscillation with continually pressed button is very "short-pulsed", i.e. it stays off pretty long (1 s) which is okay, but there is only a short on-time (0.1 s). Since keeping the button pressed is a possible usage scenario from the POV of the user, I would like to have a longer on-time. But this would require an overly big capacitor or an enormous R4.

Honestly I don't understand why it produces an asymmetrical wave form, because discharge of C1 goes over R4+R3+R5 (and RLOAD in parallel if it is there) which is only marginally larger than R4 for charging.

Is there a way to "symmetrize" this oscillator so that on- and off-time become the same?

PS: in response to your question, Jonk, some more information: ideally I would like to have a toggle-flipflop with as few parts as possible, and with zero power consumption in the off-state (aside from some leakage current of a mosfet). My impression was that the solution from EEVBlog was as close as it could get, but with the drawback of oscillating behavior instead of bistable.

When I tested it, I noticed that the duty cycle of the oscillation feels pretty much like a pathological user experience because it is like 10%. Suppose I miss the first on-period, then it turns off for a longer time and then turns on very briefly, so after I have missed it, it is practically impossible to turn it back on by just keeping the button pressed. Instead I will have to wait a certain period until the the capacitor has discharged again, until I try again to turn the thing on.

This is what I wanted to fix by "symmetrizing" the duty-cycle. If I already have to accept oscillating behavior with a short period, then at least it should allow to turn it on after missing the first period by just keeping the button pressed.

Answer 1

I think for stability and perhaps even simplicity's sake, I'd start out trying two capacitors. (I often use a MOSFET+BJT with one capacitor for a timed on-period, though, where the MOSFET+RC is vital to stay truer to the RC timing assumption.) One of them to ensure a consistent power-on state.

But perhaps something like this?

^{simulate this circuit – Schematic created using CircuitLab}

Yes, it's a high-side switch. But you can easily perform the change to make it a low-side switch, instead. (It was just easier for me to more rapidly write this out with the opposite polarity.)

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POWER-UP + INITIAL QUIESCENT STATE

Initially, on power-up, both \$C_1\$ and \$C_2\$ are not yet charged up and so \$C_2\$ initially keeps the base of \$Q_2\$ grounded and OFF. Meanwhile, \$C_1\$ might start to charge up because it isn't connected to the base of \$Q_1\$ (momentary switch, right?) But this depends upon the state of \$Q_1\$, which because of the path via \$R_5\$, \$R_4\$, and \$R_6\$ is actually pulled ON, right away (no capacitor delay involved.) So the power-up condition is reliably: \$Q_1\$ ON and \$Q_2\$ OFF. Also, in this state with \$Q_1\$ ON, both \$C_1\$ and \$C_2\$ are held "close to ground."

With \$Q_2\$ OFF, on power-up, a properly designed circuit should also have the LOAD unpowered, by default, because now \$R_5\$ is free to pull up on \$Q_3\$'s base and keep it also OFF. I think this is the desired, expected behavior.

(This assumes the current arriving at the base of \$Q_1\$ via \$R_5\$, \$R_4\$, and \$R_6\$ isn't sufficient to cause a voltage drop across \$R_5\$ that would turn \$Q_3\$ ON, of course. This is easily achieved, though, because \$Q_1\$'s collector is only sinking a very modest current determined by \$R_3\$ and therefore won't need a sizeable base current via \$R_5\$. [Easily arranged to avoid turning \$Q_3\$ ON.] When \$Q_3\$ is turned ON, of course, then \$Q_2\$'s collector must sink all of the needed base current of \$Q_3\$ and that will cause a voltage drop across \$R_5\$.)

The quiescent state should arrive with only a very small voltage across \$C_1\$ and \$C_2\$ (basically, whatever the \$V_{\text{CE}_\text{SAT}}\$ of \$Q_1\$ permits, and no more than that.) So both capacitors remain discharged, to start, and \$Q_1\$ is ON (because of the path through \$R_5\$, \$R_4\$, and \$R_6\$) and \$Q_2\$ is OFF.

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FIRST STATE CHANGE

When the momentary switch is first pressed, discharged \$C_1\$ immediately pulls down on the base of \$Q_1\$, causing \$Q_1\$ to turn OFF (for a moment.) With \$Q_1\$ OFF for a moment, \$R_3\$ and \$R_2\$ charge up \$C_2\$ to the required \$V_\text{BE}\$ of a saturated (ON) state of \$Q_2\$. So \$Q_2\$ now turns ON and pulls downward on the base of \$Q_1\$ via \$R_6\$. This keeps \$Q_1\$ OFF despite the momentary switch being held engaged. Also, with \$Q_2\$ ON, enough current is now being pulled via \$R_5\$ and \$R_4\$ that the voltage drop across \$R_5\$ turns on \$Q_3\$ and now the LOAD is powered up.

When the momentary is released, \$Q_1\$ remains OFF because \$Q_2\$ is ON and holding \$Q_1\$ OFF via \$R_6\$. Also, once released, \$C_1\$ is allowed to charge upwards now via \$R_3\$ and \$R_1\$. This voltage must be arranged by design to be enough (more than, say, \$800\:\text{mV}\$) that when the momentary switch is closed again that \$Q_1\$ will be turned ON (as opposed to this time when \$C_1\$ was mostly discharged and turned \$Q_1\$ OFF.)

So in this ON state of \$Q_3\$ (and the LOAD powered), you want to make sure that the voltage drop across \$R_3\$ (when supplying base current for the saturated \$Q_2\$) leaves sufficient voltage so that \$C_1\$ will have a sufficiently high voltage on it as it charges from that node and via \$R_1\$.

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SECOND STATE CHANGE

At this point, \$C_1\$ is charged up above what's required to turn \$Q_1\$ ON when the momentary switch is re-connected, again. Doing so now causes \$Q_1\$ to turn ON and for its collector to be pulled down for a moment and therefore discharge \$C_2\$ and turn \$Q_2\$ OFF, returning the state of affairs back to where it was on power-up.

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DESIGN NOTES

I didn't provide values for anything. That's because they depend upon your LOAD current requirements and a bunch of other details you haven't provided. But the general approach above can be adapted to most situations without much difficulty. It's just a step by step process. Your LOAD represents a certain current, requiring a certain base current and \$V_\text{BE}\$ voltage drop. This base current sets the collector current for \$Q_2\$ when it is ON. That itself requires a different base current for \$Q_2\$ to be supplied via divider \$R_2\$ and \$R_3\$. The divider node voltage must be above the required voltage needed to turn \$Q_1\$ ON, so that helps to establish their relative values. And there are other details for setting up all the resistor values. But they tend to fall out as you work through the design details.

Also, there is the possibility of the momentary switch bouncing. So you will also need to worry about debouncing the switch. There is a minimum pulse width needed to make the transition (set by your resistor and capacitor choices.) You can easily arrange this so that it ignores narrow switching pulses and requires a "long enough" hold in order to make the transition and toggle-action.

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The same topology shown above can also be made to work with MOSFETs:

^{simulate this circuit}

In the above case, \$R_3\$ can be made very much larger and this can greatly reduce the quiescent current (holding) for the OFF state of the switch. (The circuit still depends upon \$Q_1\$ being ON and \$Q_2\$ being OFF, when quiescent/OFF, so this means that your supply voltage will be across \$R_3\$ in this state.)

Circuit details such as parasitics and worsening saturation beta for \$Q_2\$ at very low collector currents will be the limitation. I would say that designing around about \$10\:\mu\text{A}\$ would be easily achievable without such considerations. And that less might be had, with some thought to them.

Answer 2

Currently C1 charges from 0 - Q3Vbe before Q3 turns on, but it only needs to discharge by 50-100mV to turn Q3 off. This makes the toggle very asymmetrical.

Replace Q3 with a P-chan FET to allow C1 to charge to a higher voltage. It now has an RC delay from 0 - VGS(th) and a discharge from V+ - VGS(th). If the VGS(th) is about half your supply you'll get close to 50% duty cycle.

Assuming you are toggling a 5V supply on/off then any FET with a VGS(th) around 2.5V would be fine ...perhaps something like a TP2104 might be suitable.

If you really want to assure a 50% duty cycle then you need a reliable toggle threshold point. easily done, but certainly more complex.

Answer 3

The problem basically goes into the direction of what Jack Creasey has noted. I found the solution only by simulating the circuit with LTSpice. Everything said below applies to my chosen operating voltage of 8 Volts.

1. Apart from the initial phase where C1 indeed charges from 0 to V(BE,Q3), C1's voltage oscillates only slightly around V(BE,Q3) ~ 0.8 Volts if the button is kept pushed and hence the output ground potential (GND) oscillates between 0 and 8 Volts (rectangularly). This is the mode I want to symmetrize the oscillation for.

2. When C1 discharges (which is the case when the MOSFET Q1 is off) the current basically takes two paths: a) over R4 and then R3+R5 and RLOAD, which for small RLOAD amounts to mainly ~R4, and b) over the base-emitter diode of Q3, the current of which is initially quite high, but decreases exponentially fast as C1 discharges more and more; so Q3 contributes almost nothing to discharging C1 and it is practically all R4's business

3. So if the output ground potential (GND) is at ~0V, C1 charges over R4, which is driven by the voltage 8-0.8 = 7.2V, i.e. I = 7.2V/1MOhm = 7.2 uA. On the other hand, if GND is at +8V, C1 discharges again over R4 but this time driven by the voltage 0.8V, i.e. I = 0.8V/1MOhm = 0.8 uA. So discharging is almost 10 times slower than charging (apart from the short Q3 base current spike)! So it's no surprise that the duty cycle is way off 50%.

My solution was to introduce an additional resistor R6 = 250 kOhm parallel to C1. So discharging C1 if GND = +8V now goes over R4 || R6 = 200 kOhm, i.e. I(C1) = 0.8V/200kOhm = 4 uA. On the other hand when charging C1, the current through R4 splits into the current through C1 and an additional current through R6 of I = 0.8/250 kOhm = 3.2 uA so the current through C1 can only be I(C1) = 7.2 uA - 3.2 uA = 4 uA. So by introducing R6 I have assured that charging and discharging goes at the same rate (at least for the small oscillations of V(C1) that actually happen).

What remains a little ugly is the base current spike through Q3, which causes some nonlinearity. I cured that by introducing a base resistor R8 of the order of magnitude of the charging resistor R4, i.e. R8 = 1MOhm.

PS: meanwhile I have done a very rough measurement of quiescent current (partial discharging of an electrolytic capacitor while battery is disconnected) which gave me <5 nA which is pretty decent in my opinion (also given that it's a breadboard build). Don't know how much of that is due to leakage inside the capacitor itself, so it's an upper bound. PS end

Pictures below show the LTSpice simulation. One can see that the current through C1 (red curve) is now symmetrical around 0 uA and as expected it has an amplitude of ~ 4 uA. Correspondingly the duty cycle of the output GND is ~50% (blue curve). The button is kept pushed at t=2s (green curve).

And finally - voila! - the normal use case, where the output ground potential GND is toggled by short button presses (instead of holding the button in the pushed state and turning GND on/off automatically, which is the "abusive" case).

Answer 4

I would like to have a toggle-flipflop with as few parts as possible, and with zero power consumption in the off-state

For small-ish loads, there's a close-ish single 8-pin chip solution that was available since the 70s :) I've built it exactly as drawn below and it works as expected. In qty 1, excluding the protoboard, the parts cost about $1, dropping to about $0.25 in qty 1k.

^{simulate this circuit – Schematic created using CircuitLab}

CD40107 does almost all we need. It is a 140mA (@10V, typical) open-drain double NAND, specified up to 20V. With a bit of external circuitry, it does all we need. For heavier loads, an external NMOS can be added of course.

There is no toggling action while SW1 is down. SW1 toggles only once each time it's depressed, and can be held down arbitrarily long without excessive current consumption or output state changes. About 15-20ms after the switch has been released, it will act again when depressed.

At room temperature, the circuit works across a 10:1 supply voltage range - from 20V down to 2V, although the channel impedance of the output mosfet goes up sharply below 5V. The quiescent current when OFF is about 1uA/V of supply voltage - so not exactly zero, but not huge either. When dropping 1V on the output NMOS, the current is about 70mA at 5V, 140mA at 10V, typical, and gets even better above 10V.

The circuit comes up in the OFF state after power-up as shown. To default to the ON state, interchange R3 with R4||LOAD.

If the 1uA/V quiescent impedance is considered too high, then a 14-pin CD4041 can handle loads up to about 30mA at 10V directly, or more with an external NMOS or PMOS. Complementary output is available, so this can be an ON-OFF switch or a toggle switch that alternates between two loads.

^{simulate this circuit}

This is a bit below $2 in qty 1, $0.50 qty 1k, at the expense of taking twice as much PCB space due to larger package (14 vs 8 pins). For the price we get more versatility though, since complementary outputs are available, and the quiescent current is about 50nA typical at 20V at room temp, less at lower supply voltages. This circuit works from 3 to 20V.

This circuit is quite suitable for operation from a 3V coin cell. In that case, R1 should be 1MΩ R2 should be 10MΩ C1 should be 100-1000pF, and C2 should be 1-10uF. It drives most light loads directly without additional parts, although a logic level N- or PMOS can improve performance during load current spikes (e.g. in pulsed load IoT applications).

In either circuit, the ratio of R2 to R1 should be 10:1. For ratios much closer to 1, excessive power consumption will occur while SW1 is depressed - that's obviously not desirable.

For operation at lower voltages, 74HC and other low-voltage CMOS logic can be used instead, with lower output impedances without the use of external MOS switches. For example, for 3V operation, the circuit takes about 3x3mm of board area. That's not a whole lot, but then there are many other solutions when low operation voltages are desirable - they take even less space :)