I am coding in Verilog a typical count-to-n-then-reset-to-0 counter. My module has the logic to increment and reset the counter.

My issue is that I don't know where the counter itself should be defined.

I could pass the counter (as inout?) to the module. That's ok, but the counter still has to be defined somewhere so it this doesn't do me any good.

Nothing else except this module should touch the counter, so I'd like to have the counter created within this module, and not passed in or out.

Is this reasonably standard, and if so, will someone point to a reference please on how to instantiate the counter?

(I'm on day 2 of Verilog, so be afraid, heh)

EDIT - Here's my code. As far as I can tell, it works. I haven't implemented DIR == REVERSE yet. Couple of interesting gotchas. The (now commented out) STEPPER=0 line was causing an error in a schematic; it thought that STEPPER was tied to ground as well as other logic.

Also, I use = instead of <= in some places involving counter - I was getting timing problems (I suppose.) The procedural assignment removed (hid?) the problem.

module cam(
    input [7:0] DIVISOR,
    input DIR,
    input SPINDLE,
    output reg STEPPER

     parameter FORWARD = 1'b1;
     parameter REVERSE = !FORWARD;

     reg[7:0] counter = 0;

    always @(posedge SPINDLE) begin
    //  STEPPER = 0;
        if (DIR == FORWARD) begin
            counter = counter + 1;
            if (counter == DIVISOR) counter = 0;
        else begin
        //  counter <= counter - 1;
        //  if (counter == (-1)) counter <= DIVISOR;

    always @(negedge SPINDLE) begin
        STEPPER = (counter == 0) ? 1 : 0;

  • \$\begingroup\$ Are you actually writing the counter logic yourself or using a Xilinx counter (or other pre-written) module? \$\endgroup\$
    – Oli Glaser
    Sep 10 '12 at 0:20
  • \$\begingroup\$ Well, I have it working now, and I did it by adding ` reg[7:0] counter = 0;` to the module, in a place where it looks like a variable. Sorry, I don't know the correct way to say it. \$\endgroup\$
    – Tony Ennis
    Sep 10 '12 at 1:27
  • \$\begingroup\$ Ah-ha! so you mean a register named counter that holds a count variable :-) I thought you meant a separate module. A couple of things - always use the non-blocking assignment <= in a sequential block (e.g. always(posedge)...) Also the = 0 part of reg[7:0] counter probably won't translate to the hardware, you will have to use a reset line for that, e.g. in an always @(posedge clk, posedge reset) you do if(reset) counter <= 1'b0; One last thing - always define the width of the assigned value (e.g. 8'b00000001 or 8'hFE) otherwise it will default to the systems bitwidth (e.g. 32/64 bit) \$\endgroup\$
    – Oli Glaser
    Sep 10 '12 at 2:26
  • \$\begingroup\$ Well, I was trying to decide between the internal counter as it is here, or having an counter module, but I prefer it as it is now. +1 on the 1'b0 thing - I had a case Sunday where what I expected to be a single line was 32 bits wide. I had some troubles with the non-blocking assignment of counter; it's used in both always sections and had an undependable value. Instead of counting by 10, for example, the circuit would count to 11. \$\endgroup\$
    – Tony Ennis
    Sep 11 '12 at 11:37

If you have two modules, and you want to use one in the other then you instantiate and connect the desired ports together.

For instance, if you have a top module with the signals clk, rst_count, inc_count and count_out and you are wanting to instantiate a (already written) Counter module with the name "MyCount" and with port names clk, rst, inc and data_out in it:

Counter  MyCount (.clk(clk), 

An excellent starting book that will take you through Verilog for synthesis (as opposed to the large part of the language which cannot be used in this way, and is primarily for simulation) is Pong Chu's "FPGA Prototyping with Verilog Examples".


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