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We're currently simulating some Xilinx AXI Stream Finite Impulse Response (FIR) IP cores.

https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf

The FIR output is not exactly expected compared pen and paper calculation. Instead, the output has some extra oscillations where none are expected. Before I brute force explore the parameter space of the various generics to understand this effect, I thought I'd reach out here and see if anyone can point me to literature addressing this issue.

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I heard back from the Xilinx people.

There's a C model for validating bit accuracy without timing. See chapter 5 of the fir compiler manual in this link

https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf

Their gcc instructions for compiling and running are accurate for rhel6. (in fact, their commands can be copied and pasted into bash. Just make sure to add the working directory to the LD_LIBRARY_PATH)

Learning this library will be a little involved though.

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