Verilog - Wiring multiple hardware instances together

Question

I am very new to Verilog and digital hardware implementation.

I want to instantiate multiple instances of a hardware block, place them side-by-side, then wire them together (ie. one block's output is the next block's input). What makes it complicated is that I want to create a 2D array-like layout of these hardware instances. Thus, each instance would propagate a signal to its lower and right-side counterpart.

This block is instantiated once below:

alg_unit alg_unit_inst (
.clk(clk),
.rst(rst),
.init(init_temp),
.in_a(in_a_temp),
.in_b(in_b_temp),
.valid_D_in(valid_D_in_temp),
);

To instantiate multiple, I am using 2 generate loops.

generate
        for (i=0; i<N; i=i+1) begin : alg_unit_generate_i
                for (j=0; j<N; j=j+1) begin : alg_unit_generate_j

                        wire init_temp;
                        wire in_a_temp;
                        wire in_b_temp;
                        wire valid_D_in_temp;

                        assign in_a_temp = A[0];
                        // other assign statements here ...

                        alg_unit alg_unit_inst (
                        .clk(clk),
                        .rst(rst),
                        .init(init_temp),
                        .in_a(in_a_temp),
                        .in_b(in_b_temp),
                        .valid_D_in(valid_D_in_temp),
                        );

           end
end
endgenerate

I need a way to refer to previously instantiated alg_unit blocks. That way, I can hook up the input signals of the alg_unit blocks generated "later" to the output signals of the alg_unit blocks generated "earlier".

Should I be assigning/storing output signals from the earlier-generated alg_unit blocks to intermediate "wire"s? Alternatively, is there a way to refer to previously instantiated alg_unit blocks?

Ie)

// alg_unit_inst[0] was a previously-instantiated block
// I feel like using the approach below may require hard-coding some instantiations ???
alg_unit alg_unit_inst[1] (
.in_a(alg_unit_inst[0].out_a),
.in_b(alg_unit_inst[0].out_b),

);

Thanks in advance.

Answer 1

With access to System Verilog I would use a 3-dimensional array:

wire [31:0] a [0:N-1][0:N-1];

Now you can wire the ports using a[x][y].
For the module at position [i][j] you can use e.g. a[i][j] at the output. To connect that to the input of the next module you can there use a[i-1][j] or a[i][j-1] or if you need to connect diagonally even a[i-1][j-1]

If ever you must use Verilog (As I had to do before System Verilog came along) you use the same method as compilers use to map an N-dimentional array on a linear memory:

wire [31:0] a [0:N*N-1];

Now the index is a combination of j and i: a[j*N+i] (If I remember correctly)