I am doing the DC analysis for a BJT amplifier using the 2N3904 transistor in a common emitter configuration. I am given +Vcc = 18V and need to find Rc to give maximum symmetrical swing. From my research I see to choose a value for Ic and then find Rc such that Rc = (+Vcc/2)/Ic. In this way the voltage at the collector i.e. Vc = +Vcc/2. However, I saw a different design which said to find Rc using Rc = ((+Vcc - V_Re)/2)/Ic where V_Re is chosen as 1V. The former approach makes more sense to me. Looking for guidance as to which way is better.
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\$\begingroup\$ Using the term "symmetrical" suggests low distortion and flat gain. By definition, this means minimal swing at the output, not maximal. The reason is that large swings imply large changes in collector current, implying large changes in dynamic emitter resistance. Compensating that means low gain. Etc. Maximum and symmetrical are opposing terms. You'll need to specify a compromise. \$\endgroup\$– jonkCommented Oct 22, 2019 at 13:30
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\$\begingroup\$ It is more of a thinking question than one with a specific answer. Ignoring saturation say your CE amp pulls the output from Vcc/2 to ground (0V); namely doubling its collector current. What happens on the other half cycle of the input signal? The collector current drops to 1/2 of its quiescent point, so the output only rises to 3/4 Vcc. Ignoring distortion, solving for the largest output swing is some what complicated. \$\endgroup\$– sstobbeCommented Oct 22, 2019 at 15:06
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\$\begingroup\$ Is this to be an AC amplifier? Will it have an Emitter resistor for bias stability, and will it be bypassed to AC? \$\endgroup\$– Bruce AbbottCommented Oct 23, 2019 at 3:22
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2 Answers
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Your approach ignores the fact that the minimum voltage that you can get at the output is not zero, whereas the approach you found takes that into account.
In other words, your simplified approach would result in a circuit that clips the negative peaks before the positive peaks reach their limit, reducing the symmetrical swing from the maximum possible value.
answered Oct 22, 2019 at 13:08
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\$\begingroup\$ This is the actual question: If the load is connected between Vc and GND, why would the minimum voltage be non zero. To me it should be zero. Could you explain why? \$\endgroup\$ Commented Oct 22, 2019 at 16:34
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\$\begingroup\$ What is the voltage on the collector at transistor cutoff? (Note: As James says, this can be influenced by the load resistance.) What is the voltage when it is saturated? Those are the two extremes you want to center on. Remember, when the transistor is approaching saturation, the current between collector and emitter is significant, and you can't ignore the voltage drops across any resistor(s) through which this current is flowing. \$\endgroup\$ Commented Oct 22, 2019 at 16:51
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\$\begingroup\$ I think I understand what you are trying to say. Correct me if I am wrong, but you are saying that with R_E in the circuit, V_CE cannot drop to zero. Now lets ignore the load, when Icc = 0 i.e. at cutoff, and assuming Ic = Ie, then V_CE = +Vcc. Then we need to look at the other end of the spectrum i.e. at saturation when Ic is at maximum. I am assuming that when Ic is at max, that V_CE = V_Re and not zero as would be the case if R_E was not in the circuit. Now is there any equation to show V_CE = V_Re when Ic is at max? \$\endgroup\$ Commented Oct 23, 2019 at 0:34
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\$\begingroup\$ Note that at all times, \$V_C = V_{CE} + V_E\$. Also, \$V_E\$ rises with emitter current and \$V_{CE}\$ never gets all the way to zero -- 200 mV is a fairly typical minimum value. \$\endgroup\$ Commented Oct 23, 2019 at 1:42
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\$\begingroup\$ Ok just to confirm I understand everything, I should be looking at the limits of the output and this is given by Vo = Vc = V_CE + V_E. So when at cutoff, i.e. Ic = 0, Vo = Vc = V_CE = +Vcc (upper limit) since V_E = I_E*R_E and since I_E is approximately Ic then V_E = 0. Now at saturation, V_CE = 0, assuming that V_E remains constant according to its DC bias value (due to the presence of a bypass capacitor acting as short to an AC variation), then Vo = Vc = V_E = IcqRe. Therefore my upper limit for my output becomes +Vcc and the lower limit is V_E and I should center on this range. \$\endgroup\$ Commented Oct 23, 2019 at 15:21
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If there is no load resistor, it makes sense to bias the collector half way between Vcc (18V) and Ve (1v in your case) for maximum collector swing in either direction. This is because, with no load resistor, the limits of the collector swing are 18V and about Ve+0.2V. (assuming the signal wiggle on the base is quite small).
In the more practical situation where the collector is coupled to a load resistance via an ac coupling capacitor it makes more sense to bias the collector to Vcc/2 = 9V for maximum collector swing in either direction. It depends on the relative values of collector resistance and load resistance but in the limit when the transistor is switched off the collector will not swing right up to 18V because it is in the middle of a potential divider formed by the collector resistance and the load resistance. If Ve is 1V and the maximum positive going excursion of the collector is, say 17V then it makes sense to bias the collector to Vcc/2 = 9V.
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\$\begingroup\$ Eventually the load resistor will be included, the only reason it is not included is so that I can set up max symmetrical swing so that my both the negative and positive portion of the output is clipped at the same level. Therefore based on what you said I should bias my collector to Vcc/2 since the load is connected between Vc and GND. I am correct about this? \$\endgroup\$ Commented Oct 22, 2019 at 17:26
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\$\begingroup\$ Also what do you mean by the collector swing. Is that Vce and V_Rc? \$\endgroup\$ Commented Oct 22, 2019 at 17:26