I'm trying to use this high voltage relay for a machine that will assist in HI-POT tests. The relay can handle about 10kVpeak according to the datasheet and I need it to handle 3.5kVrms maximum. I've run 3.5kV across the high voltage nodes in a HI-POT test on the relay and everything works as intended. While designing the PCB that will mount the relay, I looked online to see what the clearance rules are to prevent arcing elsewhere; but according to the IPC-2221B standard, the the exposed nodes need to be about 25mm apart for 3.5kV, which is already farther than the nodes on the relay are.
Can I ignore this standard or is there a different standard I should be using more suitable for HI-POT tests? How close can I actually make two exposed nodes on the PCB at 3.5kVrms?