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schematic

simulate this circuit – Schematic created using CircuitLab

The circuit has the initial condition as shown in figure. What will Vfinal be when SW3 and SW2 are open but SW1 is closed.

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  • \$\begingroup\$ Hint: Initial condition doesn't matter for Vfinal \$\endgroup\$
    – across
    Commented Mar 30, 2020 at 11:48
  • \$\begingroup\$ If both the capacitors are holding charge and I connect them back to back (series) with the supply and ground , shouldn't there be some type of charge rearrangement causing Vfinal to settle to some value? IMO it is not a simple Series capacitance calculation then. \$\endgroup\$
    – Adithya
    Commented Mar 30, 2020 at 12:45
  • \$\begingroup\$ Some song and dance happens initially, but the transient passes and it will reach a steadystate value. This final value is a simple series capacitance calculation. It settles to 1/11*V1 no matter the initial conditions. \$\endgroup\$
    – across
    Commented Mar 30, 2020 at 13:00
  • \$\begingroup\$ Some care is needed. Initial conditions affect the result, because both of the caps get exactly the same amount of charging or discharging. \$\endgroup\$
    – user136077
    Commented Mar 30, 2020 at 15:44

3 Answers 3

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Both capacitors seem to have 1V, total 2V if put to series. They are connected in series with the 1V source, so a current starts. It's in practice finite and settles soon due the losses but the current is exactly the same for both capacitors. So, capacitors get equal amount (=X) of charge, obviously negative because their final summed voltage must be 1V. The voltage change is -1V. Calculate the X from the fact that -1V must be = X*(1/C1 + 1/C2). That's X divided by the total series capacitance.

Calculate the new voltages of the capacitors by adding to 1V amount X/C1 for C1 and X/C2 for C2.

BTW no charge vanishes when both capacitors get charge X and their series connection also gets X. That's because actually when one charges a capacitor the total charge change is zero. Charge +X to a capacitor means +X to one plate and -X to the other plate.

ADD: It can be simulated if the simulator allows one to set the initial capacitor voltages. Some loss resistance must be added to prevent division by zero. See here how the voltage of node 3 drops from 1V to about 0,91V. The loss resistor is huge to make the needed time range up to full second

enter image description here

The voltage of C1 (=v(2)-v(3) in the next simulation) drops from 1V to about 90 mV

enter image description here

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  • \$\begingroup\$ Why add 1v to x/c1 and x/c2 ? Aren't we calculating the voltage in itself with the formula charge/capacitance? \$\endgroup\$
    – Adithya
    Commented Mar 30, 2020 at 17:23
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    \$\begingroup\$ 1V is the initial voltage, there was already initial charge in both capacitors. 1volt * C .That charge changes in both capacitors by amount X. The change amounts of the voltages are X/C1 and X/C2, total X(1/C1+1/C2) \$\endgroup\$
    – user136077
    Commented Mar 30, 2020 at 17:42
  • \$\begingroup\$ electronics.stackexchange.com/questions/510760/…. Could you please help me answer this using the same approach? \$\endgroup\$
    – Adithya
    Commented Jul 17, 2020 at 6:08
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The initial condition: $$Q_1=C_1U_1= 10^{-6}$$ $$Q_2=C_2U_2= 10^{-5}$$ $$U_1=U_2=1$$

The final state: $$Q=C_1\cdot U_1=C_2\cdot V_{final}$$ $$U_1+V_{final}=1$$

Solving the system: $$V_{final}=\frac{C_1}{C_1+C_2}$$

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  • 1
    \$\begingroup\$ In final state . Isn't it supposed to be q = C1/(v1-vfinal) = C2/(vfinal) . And how is v1 + vfinal =1 if v1 itself is 1v. \$\endgroup\$
    – Adithya
    Commented Mar 30, 2020 at 17:12
  • \$\begingroup\$ U1 is not V1. U1 is the voltage across C1 and Vfinal is the voltage across C2. \$\endgroup\$
    – WindSoul
    Commented Mar 30, 2020 at 17:26
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    \$\begingroup\$ I see. So initial condition doesn't matter at all in this analysis? \$\endgroup\$
    – Adithya
    Commented Mar 30, 2020 at 17:30
  • \$\begingroup\$ @Adithya The initial condition is the charge on each capacitor.It does matter. \$\endgroup\$
    – skvery
    Commented Mar 30, 2020 at 18:00
  • \$\begingroup\$ @skvery but there is no relation to the Vfinal equation to the initial charges in the capacitor. The Vfinal according to this equation is simply the ratio of Capacitances. So how does the initial condition matter? I think user287001 has got it right then. \$\endgroup\$
    – Adithya
    Commented Apr 18, 2020 at 7:45
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EDIT: See comments below the post to know why the following reasoning is incorrect.

Assuming the voltage source has internal resistance \$R\$, the voltages across the capacitors are given by:

\$v_{C1}(t) = \frac{10}{11}(1-e^{-t/RC}) + 1e^{-t/RC}\$

\$v_{C2}(t) = \frac{1}{11}(1-e^{-t/RC}) + 1e^{-t/RC}\$

where \$C = C1||C2\$

If you're any fan of superposition, a nice way to interpret above situation is to notice that the second term in each equation represents the exponential decay of initial voltage 1V on each capacitor. As you can see the initial charge on capacitors vanishes as \$t\to \infty\$, and wont matter for steadystate. (In reality, the charge doesn't vanish to \$0\$, it keeps decreasing and settles to a steady state value of \$10/11 \mu C\$)

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    \$\begingroup\$ You have assumed the final condition, this calculation starts from that assumption, so you surely get 1/11 volts. Think two equal capacitors in series, one has 1V, the other has 2V, total 3V in series. Then a 3V battery is connected to the ends. There's no current possible, but your logic states that both caps will finally have 1,5 volts. \$\endgroup\$
    – user136077
    Commented Mar 30, 2020 at 15:26
  • \$\begingroup\$ @user287001 that's very interesting, let me grab some paper and pen Looks I'm wrong here. thank you:) \$\endgroup\$
    – across
    Commented Mar 30, 2020 at 15:28
  • \$\begingroup\$ You're right! That example of equal capacitors charged to 1V and 2V connected to a 3V supply nails it! As you said I cookedup those equations by assuming the steadystate haha thanks again for pointing it out you're awesome :)) @user287001 \$\endgroup\$
    – across
    Commented Mar 30, 2020 at 15:35
  • \$\begingroup\$ @user287001 can the voltage across one of the capacitors be negative? that way one capacitor can have more voltage than the supply? \$\endgroup\$
    – across
    Commented Mar 30, 2020 at 16:12
  • \$\begingroup\$ Because when I setup a differential equation and solved, I'm getting negative voltage across C1 and more than 1V across C2. Weird... @user287001 \$\endgroup\$
    – across
    Commented Mar 30, 2020 at 16:13

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