Given this NOT gate schematic using a transistor, and assuming the power supply is a battery, won't flow from Vcc to ground discharge the battery when the transistor is on?
If yes, are there any alternatives with power consumption in mind?
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2\$\begingroup\$ Depends on the values of R1 and power is only consumed when transistor is ON. \$\endgroup\$– StainlessSteelRatCommented Aug 13, 2020 at 14:43
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3\$\begingroup\$ Yes for a suitable definition of "quick". If R1 = R2 = 1 Megohm, Vcc = 5V, and the input is '1' half the time, you're looking at 5 microamps (assuming the load is high impedance). And there are alternatives where R1 is replaced by another transistor, and you make sure only one transistor is on at once. (aka "totem pole" and CMOS) \$\endgroup\$– user16324Commented Aug 13, 2020 at 14:46
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\$\begingroup\$ I've edited the question, I was less interested in the rate of discharge and more weather any discharge would happen or not. \$\endgroup\$– Telmo MarquesCommented Aug 13, 2020 at 14:52
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1\$\begingroup\$ Someone clueless vandalized wikipedia. A FET transistor being "on" means very little in terms of power consumption unless it has a load drawing current. In CMOS that would be other insulated FET gates which have no path for steady current, so CMOS can be very nearly thought of as only drawing power when switching. Drastically less power over time than your circuit above. \$\endgroup\$– Chris StrattonCommented Aug 13, 2020 at 14:59
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1\$\begingroup\$ All transistors are inverting when used as switches. Single switches need a pull-up which defines the risetime into say 30pF load so you can choose the R value accordingly. Complementary switches only draw leakage when the other is off, so CMOS has ana advantage yet provide low impedance fast rise times. \$\endgroup\$– D.A.S.Commented Aug 13, 2020 at 15:06
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1 Answer
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Yes, this design is not power efficient.
One lower-power alternative that is widely available is the CMOS NOT gate:
In this design, we eliminated power consumption by R2 and the BJT's base-emitter junction, because a MOSFET has 0 gate current at steady state.
And we eliminated power consumption by R1 by replacing it with a p-channel MOSFET that will be in a non-conductive state whenever the n-channel MOSFET that replaced Q1 is in a conducting state (and vice versa).
In this design, the power consumption is dominated by current delivered to the load. In case the load is another CMOS gate, this current flows only during switching transitions, so power consumption can be very low indeed, especially if the gates do not change state at high frequency.
answered Aug 13, 2020 at 16:24