Why does a circuit model of N-MOSFET exhibit a finite resistance between source and gate?

Question

In the T-equivalent circuit model of a MOSFET in small signal analysis the MOSFET shows an infinite resistance between its gate and source when looking from the gate while it shows very little resistance when looking from the source.

I can't see how it can shows two different resistances like that. If the current has no path from the gate to source how it can be that it has a path from the source to gate - it's completely isolated by the SiO2 layer

One more thing is that in first glance I thought that since it's a small signal analysis the capacitive gate should be represented as a short circuit like we do with normal capacitors in the small signal analysis but instead the analysis seems to assume an open circuit in the common source configuration and a short circuit in the common gate one.

Answer 1

Mahmut S....the 1/gm "resistance" is - in fact - not a real resistor. In no case it is a quantity which exist in a real fet and could be found between G and S. It's a pure mathematical trick to make the model to obey the same equations as the other models.

In small signal AC analyses T-model works as well as the other shown models, but having a resistor between G and S is confusing and makes difficult to see the basic idea of gm - the control function between Vgs and Id. As a teacher of engineering students I do not like it, no matter it's mathematically right.

My recommendation: Don't use the T-model. Use the equivalent models with gm as a voltage-controlled current source.

Answer 2

Let us try to analyze the CS amplifier using T-model.

^{simulate this circuit – Schematic created using CircuitLab}

And the small-signal representation:

^{simulate this circuit}

As you can see we have (KVL in action):

$$v_{in} = v_{gs} + i_sR_S = i_s\frac{1}{g_m} + i_s R_S = i_s(\frac{1}{g_m} + R_S)$$

And

$$v_o = -i_dR_D$$

And because \$i_d = i_s\$ we have a voltage gain equal to:

$$\frac{v_o}{v_{in}} = \frac{-i_d R_D}{i_s(\frac{1}{g_m} + R_S)}=$$

$$ = - \frac{R_D}{\frac{1}{g_m} + R_S}$$

Now let us try to find \$i_d\$ current

$$i_d = g_mv_{gs}$$

Additional

$$v_{gs} = v_{in}\frac{\frac{1}{g_m}}{R_S + \frac{1}{g_m}} $$

Thus, the drain current is:

$$i_d = g_mv_{gs} = g_m v_{in}\frac{\frac{1}{g_m}}{R_S + \frac{1}{g_m}} = \frac{v_{in}}{R_s +\frac{1}{g_m}} $$

And now notice that the source current is:

$$i_s = \frac{v_{in}}{\frac{1}{g_m} + Rs} $$

Thus, we see that the gate current is 0A.

$$i_g = i_d - i_s =\frac{v_{in}}{R_s +\frac{1}{g_m}} - \frac{v_{in}}{\frac{1}{g_m} + Rs} = 0A $$

As you can see no gate current is flowing into the "gate" in T-model.

Answer 3

I think you're misunderstanding the models. Let's look at the T model:

^{simulate this circuit – Schematic created using CircuitLab}

The current flowing into the drain is \$g_mv_{gs}\$. The current flowing out of the source is \$v_{gs}/r_{gs} = v_{gs}/\frac{1} {g_m} = g_mv_{gs}\$. Since the drain and source currents are always equal, there is no gate current. I think the T model is drawn this way because in a BJT, \$r_{gs}\$ is \$\frac \alpha {g_m}\$, which does allow for some base current. In the hybrid-pi model, \$r_\pi\$ becomes 0 for a MOSFET, so the resistor is removed from the schematic entirely.

There is no difference between the gate-source "resistance" and the source-gate "resistance". There's no diode or anything. In this model, there's no gate current.

This version of the model does treat the gate capacitance as an open circuit. For high-frequency analysis, you have to include the capacitance between the terminals -- \$C_{gd}\$, \$C_{gs}\$, and \$C_{ds}\$. (Although \$C_{ds}\$ is small and can often be ignored.) Here's what that looks like (source is slide 74 from here):

There's still no low-frequency gate current.

Answer 4

Models which try to describe how the AC components of the voltages and currents are related with each other are not images of physical structures. Your problematic T-small signal model works approximately like a fet when only weak enough AC components are taken into the account.

Ig=0 because the voltage dependent current source makes just enough current to compensate the current that the resistor would sink from the gate in case the current source was removed. The apparent G-S resistance seen from the gate becomes infinite, no matter there's a finite resistor.

Small signal models assume certain proper DC operating point (=idle DC components of the voltages and currents) which are left out in small signal AC analysis. The trick to get those DC components right is called "biasing".