I am trying to establish an SPI Connection between a microcontroller (STM32 dev board, master) and a CPLD (slave). For a simple demo to test the connection, I was just trying to toggle the MISO pin everytime a set clock edge occurs. When I do this using the rising clock-edge, it works fine. I am using the saleae Logic 2 Logic Analyzer to view the data lines.
Here is what is looks like when I want to detect the rising edge of the clock:
As expected, the MISO line (red) toggles with every rising clock edge. However, this is what happens when changing to the falling_edge in my VHDL-code.
The pin toggles and immediately toggles back to the original state on the same falling edge, and sometimes he just misses the edges completely, not getting triggered at all. What might be a reason for this? The Pins I use are just GPIOs (also the clock. It is a slow clock of around 100 ms period), there is no filtering or anything else applied on the slave's side. The behaviour does also not change when I play around with the CPOL & CPHA-Settings in both the Microcontroller and the Logic Analyzer Software.
Edit: In the pictures I attached, the Chip Select line was high active. As soon as I change it to low active, the detection of falling edges suddenly works but the rising edges cause some glitches now. How could any of this be related to the state of the chip-select line?
