Verilog output port is high impedance (Z) when driven by a sub module

Question

I'm writing code for shifting 4-bit using carry flag for generating delay using instantiating but when I'm instantiating in top module output of top module temp1 always remain in high impedance state could you just check and tell me where I am doing wrong? In an test bench I am giving win=4'b1100 as an data...

The code follows:

module iir_model(temp1,win,clk);
    input [3:0] win;
    input clk;
    output reg [3:0] temp1;

    delay_4   a1(temp1,win,clk);
endmodule


module delay_4(data_out,data_in,clk);
    input [3:0] data_in;
    input clk;
    output [3:0] data_out;

    reg [3:0] data_out;
    reg [2:0] counter=4'b000;
    reg [3:0] temp;
    reg carry;

    integer i=0;
    always @(posedge clk)
    begin 
        i=i+1;
        if(i==1)
            temp=data_in;
        if(i>1)
        begin
            if(counter!=4'b100)
            begin
                carry=temp[0];
                temp=temp>>1'b1;
                temp[3]=carry;
                $monitor ($time," clk=%b,  counter=%b ,temp=%b ,carry=%b,data_out=%b",clk, counter,temp,carry,data_out);
                counter=counter+1;
            end
            data_out=(temp==data_in)?temp:4'b0000;
        end
    end
endmodule 

Answer 1

I believe that temp1 in the top level should be a wire, not an reg, as reg is not intended to be driven from an output port of a module.

Try changing to just output [3:0] temp1;