How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output? Or do you maybe know where I can find resources on the topic?
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2\$\begingroup\$ Normally you would not be connecting outputs together, so outputs would not strain each others. If that is not what you meant to ask, please edit the question. \$\endgroup\$– JustmeCommented Jun 19, 2022 at 13:21
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\$\begingroup\$ There are many different CMOS logic families with different drive strengths. What is the actual problem you're trying to solve? \$\endgroup\$– CL.Commented Jun 19, 2022 at 13:39
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\$\begingroup\$ @CL. Thanks for looking into my question! We started learning digital electronics in school, so I am looking for a general idea of how it strains the output, or maybe whether there might be a book or web page about it, because I have not found any resources on the question yet \$\endgroup\$– n328Commented Jun 19, 2022 at 13:47
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\$\begingroup\$ If you have a data sheet for your TTL chip, it will have input current values listed. \$\endgroup\$– JustmeCommented Jun 19, 2022 at 13:56
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1 Answer
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The datasheet (here of the SN74ALS04B) tells you how much current an ALS input needs:
The datasheet also tells you how much current an ALS output can supply:
(The absolute maximum ratings might be higher, but these are the highest output currents for which an output voltage is guaranteed.)
CMOS outputs (here of the SN74HC04) are designed to be symmetrical:
So both outputs have a drive strength that is much higher than needed for a single ALS input.
The output and input voltages also must match:
An ALS input must be pulled above 2 V when high, or below 0.8 V when low. The VOH/VOL values show that ALS and HC outputs can easily achieve that.
