Cascoded op-amp: What practically limits CMRR and input impedance?

Question

I am interested to better understand the practical limitations to input impedance and common-mode rejection ratio in cascoded op-amp structures. I already simulated quite a bit, but I am running into convergence problems for some edge cases, and I am running the risk of GIGO in such scenarios, too.

To clear up some definitions, by input impedance I mean the variation of the input bias current \$\frac{dV_{IN+}}{dI_{IN+}}\$ and, by CMRR I mean the variation of the input offset voltage \$\frac{dV_{IN+}}{d(V_{IN+}-V_{IN-})}\$. And I always refer to the generic circuit diagram below.

It contains:

• input differential pair M1 & M2
• current mirror D & CCCS1
• cascode transistors Q1 & Q2
• cascode bias V1
• tail current I1
• The depicted input differential amplifier is part of a closed-loop operational amplifier with negative feedback, e.g. a voltage follower

Questions:

1. Is it correct that both input impedance and CMRR would be infinite, if all three of the current mirror, V1 and I1 were infinitely stiff ?
2. Is it correct that the characteristics such as matching of the transistors, in contrast, don't matter ?
3. Is it correct that even at AC, the input capacitance of M1 & M2 don't really matter, as long as the cascode bias and currents remain stiff ?
4. If I am correct about (1-3), is there anything that practically (in terms of IC design) prevents a BJT op-amp from achieving something like TOhm input impedance over much of its common-mode range?

^{simulate this circuit – Schematic created using CircuitLab}