# Designing a Mod-6 synchronous counter with specific behaviors?

So a Mod-6 synchronous counter can be designed by using 3 D-flip-flops connecting the output of the previous one to the next and having the complement of the last one as the first ones input. However, we are supposed to include 2 input variables to our counter with some specific behaviors. They are as follows: $$\begin{array} {|r|r|}\hline r_1 & r_2 & Behavior \\ \hline 0 & 0 & Reset \\ \hline 0 & 1 & -1 \\ \hline 1 & 0 & +3 \\ \hline 1 & 1 & -5 \\ \hline \end{array}$$

The state table for the counter:

$$\begin{array} {|r|r|}\hline s & 00 & 01 & 10 & 11 \\ \hline s_0 & s_0 & s_5 & s_3 & s_1 \\ \hline s_1 & s_0 & s_0 & s_4 & s_2 \\ \hline s_2 & s_0 & s_1 & s_5 & s_3 \\ \hline s_3 & s_0 & s_2 & s_0 & s_4 \\ \hline s_4 & s_0 & s_3 & s_1 & s_5 \\ \hline s_5 & s_0 & s_4 & s_2 & s_0 \\ \hline \end{array}$$

I am a bit lost on how to make a counter that count in this specific manner based on input. Like I have the states in a 6-mod counter here: Now how should I draw this diagram correctly? At every state, input $$(r_1, r_2) = (0, 0)$$ will send the counter back to state $$000$$ Generally at any state there can be 4 inputs that will result in a different state. A normal counter don't really require input and will just count up or maybe down. I'm asking for some tips in how to approach this problem. For context we're only allowed to use NAND-gates, NOT-gates and D flip flops.

UPDATE: Ok so now I drew the state diagram , did the state transition table

$$\begin{array} {|r|r|}\hline s & 00 & 01 & 10 & 11 \\ \hline s_0 & s_0 & s_5 & s_3 & s_1 \\ \hline s_1 & s_0 & s_0 & s_4 & s_2 \\ \hline s_2 & s_0 & s_1 & s_5 & s_3 \\ \hline s_3 & s_0 & s_2 & s_0 & s_4 \\ \hline s_4 & s_0 & s_3 & s_1 & s_5 \\ \hline s_5 & s_0 & s_4 & s_2 & s_0 \\ \hline \end{array}$$

Then I used a type of reducing algorithm to simplify the state assignment. The algorithm is defined like this:  As an example if we take the pair $$s_0s_2$$ and check for each input which next states should be in the same or a new partition. For in 00, we see that s0 should be in the same partition, which it already is. For 01 we see that s1 and s5 should be in the same partition, since they are not included in the original pair, we create a new partition like so: $$\overline{s_0s_2} ; \overline{s_1s_5}$$ For 10 we see that s3 and s5 should be in the same group, since we already have a partition with s5 we simply add s3 to that group:

$$\overline{s_0s_2} ; \overline{s_1s_5s_3}$$ For 11 we will have that s1 and s3 should be in the same group which they already are. So now we apply the same idea that we did to s0s2 to s1s3s5. We look for each input of this 3-partition where the next states will be. For 00 we get that s0 should be in a partition which we already have, s0s2. But now for 01 we get that s0, s2 and s4 should all be in the partition, and since we have s0s2 we add s4 to that group resulting in:

$$\overline{s_0s_2} ; \overline{s_1s_5s_3} \longrightarrow \overline{s_0s_2s_4} ; \overline{s_1s_3s_5}$$

This 2-part partition can now be coded with 1 bit. Like: $$\overline{s_0s_2s_4}: 0$$ $$\overline{s_1s_3s_5}: 1$$

The problem is basically that when doing this algorithm and coding the different partitions like above and a second 3-part partition like this:

$$\overline{s_0s_3} ; \overline{s_1s_4} ; \overline{s_2s_5}$$

Coded like: $$\overline{s_0s_3}: 00$$ $$\overline{s_1s_4}: 11$$ $$\overline{s_2s_5}: 01$$

This will yield a state assignment table looking like this:

$$\begin{array} {|r|r|}\hline s & q_1 & q_2 & q_3 & 00 & 01 & 10 & 11 \\ \hline s_0 & 0 & 0 & 0 & 000 & 101 & 100 & 111 \\ \hline s_1 & 1 & 1 & 1 & 000 & 000 & 011 & 001 \\ \hline s_2 & 0 & 0 & 1 & 000 & 111 & 101 & 100 \\ \hline s_3 & 1 & 0 & 0 & 000 & 001 & 000 & 011 \\ \hline s_4 & 0 & 1 & 1 & 000 & 100 & 111 & 100 \\ \hline s_5 & 1 & 0 & 1 & 000 & 011 & 001 & 000 \\ \hline \end{array}$$

And HERE is where the problem lies. You see the output of the circuit behaves exactly like this table. The issue here is that the state transition is working the way it shall. But the encoding of the partitions does not get the result. The fact that the output is corresponding to the q1, q2, q3 should mean that I should just code it 000, 001, 010 etc and do the Kmaps from there.

Update with solution.

So thanks to James I added a final output logical block. I had this table with the states binary codes and the outputs I wanted them to have:

$$\begin{array} {|r|r|}\hline q_1,q_2,q_3 & {q_1}^+,{q_2}^+,{q_3}^+ \\ \hline 0,0,0 & 0,0,0 \\ \hline 1,1,1 & 0,0,1 \\ \hline 0,0,1 & 0,1,0 \\ \hline 1,0,0 & 0,1,1 \\ \hline 0,1,1 & 1,0,0 \\ \hline 1,0,1 & 1,0,1 \\ \hline \end{array}$$

So from this I got these boolean expressions:

$${q_1}^+ = {q_1}^´q_2q_3 \vee q_1{q_2}^´q_3$$ $${q_2}^+ = {q_1}^´{q_2}^´q_3 \vee q_1{q_2}^´{q_3}^´$$ $${q_3}^+ = q_1q_2q_3 \vee q_1{q_2}^´q_3 \vee q_1{q_2}^´{q_3}^´$$

Conneted and tested. Gives the desired behavior for my machine. Question for analysis now is: Is this extra output block more effort than having the states being encoded in their expected output?

• Note that the counter described in your first sentence does not have the states shown in your diagram. The instructions seem to imply that you want a binary counter. Start by writing down the state transition tables for each of the four input combinations. Oct 7, 2022 at 12:07
• I’d probably start by drawing 4 state diagrams - 1 for each input combination. Then translate into one state table. Simplify are derive your logic from the table or derive your sum of products then simplify. Oct 7, 2022 at 12:09
• @Kartman Ok! Since it's synchronous I don't need to bother in making it race-free right? Oct 7, 2022 at 12:11
• Subtracting 5 is the same as adding 1 (maybe this makes it easier). I'd use a plain modulo 6 counter and take the output to some adders where I'd do the math (respecting that their might be two invalid answers that need skipping). Oct 7, 2022 at 12:22
• @Andyaka Yes was thinking on that. Not sure we have enough gates to make a bunch of full adders. And adders were the subject of the last lab session. So don't think that's our goal. Oct 7, 2022 at 12:30

You need to learn how to design a state machine. You say that it will be synchronous which implies that the outputs will only change at the time of the active clock edge and so the outputs will not respond to changes on the r1,r2 inputs inbetween active clock edges. This suggests that you need a Moore Model instead of a Mealy Model.

The usual way to proceed is to draw a state diagram (This is perhaps the part which takes most effort and needs to be got right or all of the following work will be in vain). Next write out the state transition table and then simplify for each of the 3 D-type flip-flop inputs (next state variables) using Karnaugh maps. You'll need three 5-variable Karnaugh maps for the D inputs. Lastly implement the simplified expressions using the appropriate logic gates to create the state machine.

There are two usual ways to make the system cope if it gets into states 110 or 111. Firstly use a power-on-reset for the D-type flip-flops to force the system into a known state or alternatively include the states 110 and 111 as present states in the state transition table so that if the system gets into one of those two states it will be forced to a known state at the next active clock edge.

Quite a lot of work and a good deal of effort required to get it right. I don't know how much experience you have but, solved in this way, it's not really a beginner's problem. The input is r1 & r2. The register is the three D-Type flip flops with the next state variables being applied to the D inputs and the present state variables coming from the Q outputs.

You'll see in my diagram that the outputs are not immediately affected by changes at the inputs (r1,r2). Outputs changes can only occur at the time of the active clock edge. This is the Moore model. You can see a block diagram of the Mealy model below which shows how the outputs can be immediately affected by changes at the inputs.

So, you should be able to see that the only difference between my two diagrams is that the Mealy model has a direct path from the inputs to the output logic. The above diagrams are generalised forms of the Moore and Mealy state machines. In your problem, and because it's a Moore machine, you won't need the output logic block and you will be able to use the Q outputs from the D-flip flops (present state variables) as your system outputs. I have amended my text above to concur. This will give you a final circuit more in line with your sentence "the idea of a Modulus counter being a number of flip flops connected in series".

I don't know (or understand) what all that partitioning business is about, never come across that before. I go straight to what you refer to as the "state assignment table". Just list the 8 states in the left hand side of the table going down from q1q2q3 = 000 to q1q2q3 = 111 in ascending order, then in the right hand side of the table put in the 4 columns of 3 bit next state values, each 3 bit column corresponding to an r1,r2 input. Each 3 bit column on right hand side should be labeled q1+,q2+,q3+ (these are the D1,D2,D3 inputs of the flip flops) and you now need to do a 5-variable k-map for each of q1+, q2+ and q3+ with the two axis on each of the k maps labeled as q1q2q3 and r1r2. So each of the three k-maps will have 32 cells. The bottom two rows on the right hand side of the "state assignment table" will contain X's (don't cares) because q1q2q3 = 110 and 111 can't, in theory, happen.

You'll need to find out how to implement 5-variable k-maps where some of the groupings can be obtained by vertically stacking the two halves of the k-map or, alternatively, by using symmetry between the two halves. Which you use depends on how you label the axes.

• I have done a bit of it now. Question now is how the D flip flops should be connected? Provided a design but not sure if that's right? Oct 8, 2022 at 14:02
• I have included the circuit from Logism. I want to think I have done it right. But since the behaviour is wrong, There is something obviously. Oct 8, 2022 at 20:03
• I feel like my circuit still is in Moore form. Oct 8, 2022 at 20:05
• @felix9801 In my past experience of designing similar and more complicated systems I have often found that the final system behaviour is incorrect (I have to admit!). Then it's a matter of checking and perhaps rechecking through the design procedure thoroughly to try and locate the error(s) in my work.
– user173271
Oct 8, 2022 at 20:16
• This is what I'm basing my model on. It has different behaviour. But these are the steps I've followed. Partitioning the states, doing the 3 3d-Kmaps. youtube.com/watch?v=1hBwB_aggMQ Oct 8, 2022 at 22:01