Realize that all MOSFETs have negative tempco of Vgs(th) in linear mode, at least over a significant portion of their operating range. Thermal runaway is a necessary and ever-present characteristic of all MOSFETs.
The question is not whether it can, but under what conditions it will run away.
The thing with vintage (lateral) MOSFETs is, they can have a neutral to positive tempco, or source resistance dominates (degenerating transconductance and with a +TC), at fairly modest currents, well within the power dissipation rating. And with fairly generous power dissipation ratings relative to the V,I capacity (i.e. the die area is large, power density is low), they're easy to heatsink adequately.
That doesn't mean runaway was impossible: just that a situation has to be more contrived. For instance, say you put two in parallel, matched, but no heatsinking (or even with insulation), and run them up. One inevitably overheats, perhaps at just a few watts, perhaps tens (but perhaps not hundreds, for which you'd need a proper heatsink to reach anyway). That's contrived, as I said, and far from good practice -- but consider the thought experiment: for any given transistor, there is some thermal conductivity between portions of the die, and therefore some temperature differential in response to a power differential. With discrete dies, we've simply dialed that differential up to the maximum.
So, we conclude that the ratio of tempco to differential thermal resistance is key.
The fact that, on a monolithic device (single die), on a thick copper back plate, the thermal conductivity is quite high, means that fairly poor tempco and high power density are still reasonable. Thus we have denser devices still behaving well.
Come to think of it, I wonder if that's the trick: SuperJunction transistors have higher power density than ever, but it may be the die thinning dominates, and the copper backplane is more conductive than pure silicon, and the die smaller for given V,I ratings anyway, so the temperature drop across the die can still remain modest. (This comes from the peculiar observation that a lot of SJ MOSFETs offer full DC SOA.)
Regarding low voltage types -- planar vs. trench -- it could be that the curves are subtly altered, I don't know about this specifically. But if a counterexample would do, they certainly exist: consider IRFP4768PbF | Infineon, the SOA is limited at a mere 7V (and 70A..!). It is a "HEXFET", probably the "advanced generation" (7th?), which would be finest pitch in the family (cell size in the low 100s nm perhaps?), before moving to trench and SJ.
Incidentally, I've never seen even-numbered HEXFET generations; I wonder how much of that is real development versus marketing? Also, are there still new HEXFETs being released? I don't recall.
In any case, it's certainly possible for planar devices to run into such limits, as-is, given ideal circuit connection (i.e. not paralleling naively) and heatsinking. Some of it varies with design, I imagine they can optimize for SOA, but clearly there are examples where they optimize without regard for that, and indeed make some pretty awful SOAs in the pursuit of maximum switching area.
Mind, this is all observational, based on data books, datasheets and appnotes, and occasionally informed by die photos. Incidentally, past... generation 5 I think?, HEXFETs haven't been "hex" at all, but the same stripe layout everyone else uses. It's probably not possible to achieve high density and yield on finer pitches with the traditional hex layout. AFAIK, it's still planar: the same self-aligned gate process, lateral channel, and vertical drift region that's always been used, just the arrangement is in stripes rather than a grid.
(Incidentally, SJ is planar too, on top I mean, at least as far as I've seen from diagrams. A planar structure interfaces well with the SJ pillars, and, I suppose, the higher current density enabled by a trench structure just doesn't matter when these devices are currently limited by the pitch of the pillars themselves.)
But yeah, compare that to trench: the channels can be packed that much more densely (roughly speaking, twice per cell), and maybe the tempco is different, I don't know.
Die thickness (and thus thermal resistance between regions) will be comparable for all low-to-medium voltage types: limited by mechanical handling probably. The ultimate limit is the depletion region thickness, perhaps a couple µm; but a legitimately thin film of Si isn't very practical for handling, heh. I believe they are largely made on n+ doped wafers, i.e. highly conductive substrate, so the thickness doesn't matter too much, and then the drift region and active circuitry are epitaxied then diffused on top (n- drift, p channel/substrate, n+ source).
(This contrasts with SiC devices, where the maximum doping level just isn't very high, or dopant activation at operating temperatures is incomplete; die thinning is done with much greater pressure there. This is basically why SiC schottky for example have such an exaggerated resistive slope to them -- this even after best efforts to grind away the excess!)
This is very much a question that should be asked of an active semiconductor engineer -- but there are very few indeed posting here, that I know of, let alone that are able to discuss current or even past technology. For more detail, you'll have to peruse academic papers, or find researchers or engineers working on this stuff (and willing to talk about it). Cheers.
