What determines the maximum clock rate for a CPU?

Question

What factors determine the maximum CPU clock rate? A 6502, for instance, clocks in the megahertz range, while an Intel x64 chip typically clocks in the gigahertz range.

All things being equal, if the 6502 is manufactured using the same materials, nanometer rescaling, and the same photolithography process as the latest x64 CPU, it's conceivable it should also be capable of running at gigahertz speeds, especially considering the 6502's simpler design and lower gate count.

Am I missing other factors, such as the CPU design, which could limit its maximum clock rate?

Answer 1

First you must consider multiple things. The logic itself that makes the CPU, the technology (used to implement the logic), and the architecture used to design the logic. And to be able to deliver it at certain price point.

Sometimes they are intertwined. You must use some technology for some reason for example target price, and the logic is implemented so that it can be realized with the technology, and some architecture may be used because technology dictates what kind of architectures can be implemented to be cheap or small enough to fit into some package.

Basically a CPU is just bunch of logic doing whatever it is wired to do. So in the end, you simply want to implement the logic what makes a CPU. The logic is ideal and can be represented as just equations how other wires affect each other.

The technology you have available defines how the equations need to be physically implemented, as generally you can't have e.g. an equation for single output wire that depends on arbitrarily large number of input wires. The equation must be divided into maybe larger number of logic gates that are physically realizable with the technology and these interim outputs must again be combined to get the final output you want.

Since the original 6502 was made using NMOS technology, it defines the structures that need to be used to build larger equations. NMOS in general uses just NMOS transistors, they can pull low strongly, but for pushing a signal high, either a passive resistor can be used, or turn an NMOS into a controllable pull-up resistor. Using resistor or NMOS for pull-up is slow and wastes power.

Another twist in addition to the NMOS logic is that you need large amount of NMOS transistors to build static logic, and since your logic anyway needs a clock to run, you can use more efficient structures which use less power and less transistors if you use dynamic logic, which generally is the main reason why the 6502 wants two clock signals that are out of phase and non-overlapping.

So in light of this, the original 6502 is implemened in dynamic logic using NMOS technology.

It can't be implemented as-is in modern technologies as they are not compatible.

To implement the same bunch of logic in CMOS, you need to redo all the logic equations again with structures that make sense to do in CMOS. CMOS has both NMOS pull transistors and push transistors.

And while you can do dynamic CMOS structures, even the same dynamic logic needs to be implemented differently than dynamic NMOS logic.

And since it is possible to have efficient static CMOS logic, the same logic can be implemented with rules for static CMOS logic too - which is why some 65C02 can work at arbitrarily low or even be halted by stopping the clock and it consumes very little DC current. And since same logic equations could be used to describe how the CPU works, it would be possible to have an exact clock-cycle compatible CMOS version of original 6502.

So the point is, it does not scale as-is, and to reimplement a 1 GHz 6502 may or may not be possible as the required logic atructures needed may simply not be realizable to support 1 GHz directly. It might be possible to implement the same bunch of logic as smaller pipelined stages, so it may require again re-implementing the same logic with structures compatible with modern technology to push the clock speed up to 1 GHz, still being clock cycle compatible.

But it does not stop there either. If you want to just have as fast as possible CPU that is 6502 compatible, you can't use the original slow logic equations which used multiple clock cycles per instruction, you need to stop using the same logic and simply derive a new set of logic equations that can maybe execute all instructions in a single clock cycle.

As the original 6502 takes 2 to 7 clock cycles to execute a single instruction, an implementation that uses single cycle instructions could itself be 2 to 7 times faster depending on what code you execute.

That's what happened to Intel 8051. It was redesigned as single cycle IP core that can be embedded onto silicon to handle chip hardware. As one instruction cycle takes 12 clock cycles, the resulting 8051 will be on average 56x faster with the same clock. And it can run at 300 MHz which equals an original 8051 clocked at 17 GHz.

As 6502 opcodes are mostly simple and could map to single cycle x86 instructions, even converting the matching opcodes to x86 opcodes gives you a significant boost, as 1 GHz x86 could in theory equal to a 2 to 7 GHz 6502. I recall one emulator that boasted this kind of performance.

What the emulator shows that it might not be worth it to reimplement a 1 GHz 6502 chip in hardware as even software emulator running of sub-GHz host CPU can emulate a 6502 which would be much faster than original 6502 clocked at GHz.

Answer 2

The present x86 isn’t made from the ‘same process and materials’ as the 6502, any more than a modern automobile and a Model T are.

Your point is taken that they’re both based on silicon, just as cars are still mostly stamped sheet metal, even today. Nevertheless, decades of continuous process and materials development have steadily improved silicon performance. Yes, there were some explorations into other base materials for CPUs (notably gallium arsenide) but in the end silicon won the day.

We’ll get to your 6502 thought experiment in a moment. First, let’s discuss what’s changed since 1977-ish.

The biggest silicon improvement? Channel length (feature size generally) makes a huge difference in CPU performance. Contemporary CPUs have channel lengths about 1000x shorter than the 6502:

• 6502: 8um
• Typical CMOS today: 7nm

This key difference affects gate delays, which ultimately determine the achievable cycle time. Having smaller features also reduces capacitance and wire delays, further boosting speed.

Also note the 6502 was an NMOS part (CMOS ones came later) which also puts it at a disadvantage over contemporary CPUs. But really, it’s the smaller feature size that makes the difference.

Now, could the 6502 be run at GHz speeds in a modern process? Very likely, but it might require some tweaking, especially the introduction of some pipelines to break up delay paths.

And note that the 6502 I/O speed also limits its performance: some onboard memory would be needed to break that bottleneck. Modern CPUs have buffer memories and/or caches with fast, low-latency paths to the CPU.

To give you an idea of what’s possible, here’s a 6502 implemented in an FPGA, that runs at 100MHz: https://blog.adafruit.com/2021/10/13/the-100-mhz-6502-microprocessor-fpga-emulation-vintagecomputing/ One key detail: at startup, this device copies the entire 6502 address space to internal RAM, speeding things up considerably. Only I/O makes it out to the pins.

As it is, 100MHz on a Spartan-6 is pretty good for that FPGA, hinting that 6502 decoding and execution are pretty efficient. This would bode well for a custom 6502 ASIC hitting GHz speed.

Answer 3

Clock rate is ways limited by the longest combinational path length. This is the longest chain of gate logic, that is expected to finish and return its result to the next register within a single clock cycle.

This can be notably improved by two means:

1. Make gate logic faster. Up until approximately the 100 nm-ish nodes, each full node downscaling allowed a 30-50 % speed improvement. Later, this has slowed because one had to reduce power input as one scaled down further, with smaller nodes allowing less power per gate to limit power dissipation areal density.

2. Make the path shorter in the design, by introducing intermediate registers and running sections of the long path in parallel. This is called pipelining. It has drawbacks in that it requires greater planning by the instruction scheduling to keep all execution units filled. That is why it is not taken to the extreme, (or fails when it is - Intel Netburst).

My guess is: If someone wanted to re-implement an ancient design targeted at low bit width, with modern CMOS at modern power density. It has simpler instructions, but also less pipelining, so ends up properly similar or at slightly higher clock frequency.

Answer 4

It's really the overall timing of the different hardware sections processor, as things like adders/multipliers/pipelines and other instructions have gate delays. The gate delay of the hardware for an instruction or pipeline has to be shorter than a CPU cycle for the hardware of an instruction. If you run the CPU cycle shorter than the delay, the 'answer' that is given in the hardware will not be deterministic (and not be complete or give a meaningful answer).

Answer 5

Yes. There are many other things - i.e. clock propagation - basically, the size of the clock tree matters. Small silicon areas permit to use a smaller clock distribution network, which can lead to faster clock rates.