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A common 2nd order Delta Sigma ADC topology is shown for example in Wikipedia. Here, if you omit the left summing node and the left Integrator, a conventional 1st order Delta Sigma ADC emerges.

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Now consider the following implementation of a 1st order Delta Sigma converter:

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The three left components (R10, R11, C6) realize the summing and integration function. The comparator and its positive feedback branch realize the Quantizer and DAC functions. This works nicely and I have used it many times.

I now attempted to extend this architecture to realize a 2nd order modulator, by adding another summing and integration node:

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The feedback resistors have been set to ensure a signal transfer gain of 1, and the integration capacitors have been set to obtain a similar switching frequency.

The PWM waveform that comes out of this supposedly 2nd order modulator looks almost exactly like the one from the previous 1st order modulator. The typical features of a 2nd order modulator are missing, such as double pulses or in general a seemingly non-constant duty cycle. Below is an example of the output of the first and second schematic, which are nearly identical apart from a minor frequency difference.

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And, finally, here is the spectra of the two outputs, while modulating the same input, which is a 50 kHz, 0 dBV sine wave. Both versions show a roughly 20 dB/dec noise increase towards the natural modulator frequency. The flat part of the noise at low frequencies is an artifact from the resampling that LTspice does in order to compute the DFT, I guess.

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Why isn't this behaving as a 2nd order Delta Sigma modulator?

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    \$\begingroup\$ I believe the addition you made doesn't constitute an extra integrator. \$\endgroup\$
    – Andy aka
    Commented Jun 1, 2023 at 12:47
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    \$\begingroup\$ The test of a 2nd order modulator is not 'double pulses' or a seemingly non-constant duty cycle, but the spectrum of the output (it rises at 40dB/decade instead of 20dB), and the time behaviour of the two integrators. You have a simulation setup, take the spectrum of the output, and/or plot the time evolution of the two integrators, and post the results in your question. \$\endgroup\$
    – Neil_UK
    Commented Jun 3, 2023 at 9:59
  • \$\begingroup\$ @Andyaka could you elaborate what it takes to be called an integration stage then? After some googling I got a tentative hint that an RC circuit represents a "delaying integrator". Otherwise I will try to add what Neil asks today, but the time-traces and spectra are really similar. They essentially overlap. \$\endgroup\$
    – tobalt
    Commented Jun 5, 2023 at 4:31
  • \$\begingroup\$ @Neil_UK I have added the time and frequency information. \$\endgroup\$
    – tobalt
    Commented Jun 5, 2023 at 11:24
  • \$\begingroup\$ I'm reluctant to spend the time to crank up my simulator. What's the actual measured frequency response of the feedback part of the circuit you've shown? Is it first or second order? Whenever I've implemented noise shaping sigma delta, I've always used a gain-block integrator for every order I wanted, \$\endgroup\$
    – Neil_UK
    Commented Jun 5, 2023 at 12:21

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I don't think "The comparator and its positive feedback branch realize the Quantizer and DAC functions." is correct and this part of the circuit is what is causing your unexpected results. Looking at the wiki page and sources it seems like there is always a clock input, and the feedback coming from the 1 bit DAC is always aligned to this clock. So you need some kind of a clocked s&h buffer/d flip flop.

If you remove R14, R10, U2 and the rest beyond that, you should be able to verify the second integrator is working. I get the intuition that your feedback path circuit is acting as a sort of first order delta sigma modulator that converges quickly and dominates the behavior of everything. So you don't want that involved at all if you are testing just the integrators.

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  • \$\begingroup\$ Thanks! I just tried adding a S&H stage after the comparator. I made sure, the clock is such that the switching frequency is roughly near the non-S&H version. In the 1st order circuit this leads to a significant change of the spectrum. The noise rises at a steady 20dB/dec now. Overall, this clocked version is much much worse than the asynchronous version. I guess the standard descriptions of Delta-Sigma modulators only apply to clocked versions. Even with clocking, my "1st and 2nd order" modulators still are identical in behavior. I will experiment more. \$\endgroup\$
    – tobalt
    Commented Jun 7, 2023 at 6:56
  • \$\begingroup\$ Upon further reading, I now believe that my 1st implementation is not in the scope of Delta Sigma literature. This field addresses clocked modulators. The clocking imposes that only certain analog values such as 1/2, 1/3 or 2/5 can be respresented with a short pulse sequence. Intermediate values produce noise at other frequencies. The "analog" modulator I made doesn't have this issue. Its duty cycle is always an exact representation of the input, so higher order modulation is meaningless to it. \$\endgroup\$
    – tobalt
    Commented Jun 8, 2023 at 7:27
  • \$\begingroup\$ But this still leaves me with the question (when I do implement the clocking) what I have to do to establish a second order delta sigma modulation. I have tons and tons of papers and articles about continuous-time delta sigma modulators. As far as I can tell they do nothing different. \$\endgroup\$
    – tobalt
    Commented Jun 8, 2023 at 7:29
  • \$\begingroup\$ Quantization of the input is one of the features of an ADC. The output of a delta sigma modulator should be a clocked digital sequence of bits. If the output duty cycle of frequency varies at all continuously, then it isn't really an ADC anymore and could introduce new problems like timing violations if you try to use it as one. If you link some of this continuous time papers I can take a look, but from what I can tell so far I think continuous time only refers to the filter/integrators and input, not the feedback path. \$\endgroup\$
    – R McHenry
    Commented Jun 8, 2023 at 17:27
  • \$\begingroup\$ Yes you are right. My modulator is not an ADC. When I use an analog lowpass, it is faithful to the input, but if I just take discrete asynchronous sample from it, it ends up actually worse than the first order clocked DS ADC, because the sampling error happens outside the feedback loop of the modulator. My main remaining question is though, even when I introduce a clocked S-H stage in front of the comparator (as is shown in papers for CT-DS-ADCs), I obtain proper first order behavior always, even when I copy 2nd order designs to the letter (using the bv behavioral voltage sources). \$\endgroup\$
    – tobalt
    Commented Jun 8, 2023 at 17:36

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