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So I have been studying about logic gates designed using the CMOS family and in my professors notes it says "Move NMOSFET-B closer to output node, without changing the functionality , to reduce the parasitic capacitance and thus the fall time delay", I couldnt come to an understanding as to why this happens. The diagram of the NAND gate as a reference

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  • \$\begingroup\$ Closer than what? This is clearly a physical layout question. What two layouts are we considering? \$\endgroup\$
    – Dave Tweed
    Nov 1, 2023 at 11:48

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I guess your professor meant that if NMOSFET-B is closer to the output, the routing X will be smaller and hence parasitic capacitance on that net will be small and it will improve falltime.

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The question is unclear. The canonical layout of a CMOS NAND gate looks like this:

CMOS NAND gate

(from Wikipedia)

The A and B inputs are similar lengths of poly, and the node "X" is simply the common channel between the two lower transistors. Is the professor suggesting that there is a better layout than this, or is that his way of describing this layout?

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