I would like to know why does the IPC 2221 standard requires spacing much larger than the ones necessary from dielectric strength consideration.

My first question is related to the distance d_1 of the sketch below (distance between copper traces in same layers covered by solder stop.)

PCB sketch

The datasheet of the Coates Imagecure XV501T solder stop material gives a dielectric strength of 160 kV/mm:

enter image description here

Therefore, a maximum voltage of 16 kV could be sustained between two traces 0.1 mm apart, am I right?

My second question is related to distance d_2 of the sketch above (distances between copper traces of opposing outer layers.) In the datasheet of the Isola Duraver DE104 FR-4 material a dielectric strength of 29 kV/mm is specified:

Datasheet FR-4

Given the standard thickness of 1,55 then a maximum voltage of 44,95 kV could be sustained, am I right?

If my computations are correct, then why does IPC-2221 require much much bigger spacing between conductors? (B1 is for internal conductors and B4 are external coated conductors.)


Are they taking into account worse materials, or is it because of safety margins?

  • \$\begingroup\$ Top surface will be subjected to pollution. Inner ones do not. Will you apply high voltage continuously or just a quick test? \$\endgroup\$
    – winny
    Jan 18 at 11:55
  • \$\begingroup\$ MEC does not consider soldermask as insulation, regardless of published material properties. If your board manufacturer can guarantee soldermask thickness then you could probably up-rate a bit but I would build in a design factor of at least 2. \$\endgroup\$
    – vir
    Jan 18 at 12:07
  • \$\begingroup\$ @winny Voltage will be continuously applied. Solder mask should provide protection against pollution \$\endgroup\$
    – Ken Grimes
    Jan 18 at 12:38
  • 2
    \$\begingroup\$ If continuous, the dielectric breakdown is not to be designed for as it's the very short impulse voltage it can withstand. You will have partial discharge, electro migration and/or tracking before that if applied continuously. At 16 kV, I would apply well over 100 mm spacing, depending on CTI of the PCB. \$\endgroup\$
    – winny
    Jan 18 at 12:55
  • 1
    \$\begingroup\$ Do not depend on soldermask for insulation, that is not its purpose. Same with conformal coating. Do you have any connections to the board? How are they insulated? Do you understand that you must avoid sharp points at these voltages because they can create local high electric fields? \$\endgroup\$
    – Mattman944
    Jan 18 at 14:15

1 Answer 1


Creepage will reduce dielectric strength over time.

And creepage will proceed along the easiest trace, not necessarily the direct line. In your example, this is either along the board/resist interface with its undefined properties, or through thin parts of the resist and along the top surface.

The distance rules are there to provide safety margins despite these creepage effects.


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