High-voltage PCB design and IPC 2221

Question

I would like to know why the IPC 2221 standard requires spacing much larger than necessary from a dielectric strength consideration.

My first question is related to the distance d_1 of the sketch below (distance between copper traces in same layers covered by solder stop).

The datasheet of the Coates Imagecure XV501T solder stop material gives a dielectric strength of 160 kV/mm:

Therefore, a maximum voltage of 16 kV could be sustained between two traces 0.1 mm apart, am I right?

My second question is related to distance d_2 of the sketch above (distances between copper traces of opposing outer layers.) In the datasheet of the Isola Duraver DE104 FR-4 material a dielectric strength of 29 kV/mm is specified:

Given the standard thickness of 1.55, a maximum voltage of 44.95 kV could be sustained, am I right?

If my computations are correct, then why does IPC-2221 require a much wider spacing between conductors? (B1 is for internal conductors and B4 are external coated conductors.)

Are they taking into account worse materials, or is it because of safety margins?

Answer 1

Creepage will reduce dielectric strength over time.

And creepage will proceed along the easiest trace, not necessarily the direct line. In your example, this is either along the board/resist interface with its undefined properties, or through thin parts of the resist and along the top surface.

The distance rules are there to provide safety margins despite these creepage effects.

Answer 2

Soldermask, if applied solidly as an approved insulating coating, has excellent dielectric rating, as you can see.

This is rarely the case in practice, however. Soldermask is applied as a liquid, prone to pinholes, bubbles, and variable thickness as surface tension pulls it over the uneven surface of traces; as well as printing errors, handling blemishes, and it can flake off due to handling or perhaps soldering too, particularly the weaker grades popular among proto fab services.

Therefore, for almost all cases with standard fab, the insulation between traces must be treated as air, plus creepage along the board surface. See safety regulations/standards such as IEC 62368-1.

If you need high insulation rating, consider a custom build -- ask your PCB fabricator or assembler for an approved coating process, whether soldermask based, conformal coating, or partial potting compound, or consider potting the thing whole in an enclosure (use vacuum to prevent voids!).

Or, similarly: the PCB material itself may count as a cemented joint. The ratings between layers, and between traces on inner layers, can be considerably higher than on the surface. Mind that the current rating tends to be lower (traces are surrounded by thermal insulation too), and the voltage rating depends on approvals -- I've seen materials that are not rated as a "cemented joint" on inner layers, and therefore must be designed with creepage and clearance still in mind!