I understand that if I use a FET as a source follower, the signal will be slightly attenuated due to the fact that there is some small inherent resistance in the FET, creating a voltage divider effect between the FET's internal resistance and the source resistor Rs.

In the student manual for 'The Art of Electronics' (Horowitz), he shows a diagram that implies using a current source in the place of Rs can create a circuit with no attenuation. As is the case with many diagrams in this book, his explanations kind of glaze over what is going on, without going into great detail.

In this particular situation, he's aiming to have 2 mA Id current flow. He picked the 1.4k resistor from the curve of ∆Id vs ∆Vgs given this current requirement - making Vgs = -2.8V.

In the diagram, he traces his reasoning: (1) Here drops Vgs, (2) so same current also drops Vgs here ... so Vout = Vin.

I get why Vgs drops across these resistors, but I don't understand how he arrives at the conclusion that Vout = Vin. In particular, I don't see why the voltage at the source of the top FET should be equal to Vin+Vgs.

Can anyone shed some light on this confusion?

Here's the diagram:

enter image description here


First, \$v_{in}\$ is an AC signal voltage while \$V_{GS}\$ is a DC bias voltage. These are treated separately.

From a small-signal perspective, the current source (lower FET) is effectively an open circuit so there is effectively no voltage division for the AC signal. This is why \$v_{in}\$ appears at the output node unattenuated (assuming the output node is connected to an effectively open circuit).

From a DC bias perspective, the gate of the top FET is at (presumably) zero volts so the source, which must be more positive than the gate, must be at 2.8V (using the values in the book and assuming the FETs are identical).

However, note that this is not \$V_{GS}\$ since, in fact, \$V_{GS}\$ for both FETs is -2.8V. In other words, the voltage at the source of the top FET is $$v_{in} - V_{GS}$$


Nice circuit. To answer your question:

First of all lets agree on the basics: This kind of FET conducts when \$V_{GS}\$ is zero, and the current diminishes when the gate starts being negative with respect to the source (\$V_{GS}<0\$), down to a point where it is turned off.

Secondly, it is assumed that both FETs are identical, so that the same \$V_{GS}\$ produces pretty much the same current on both FETs.

The bottom FET is basically a current sink, designed to sink 2mA (but exactly how much it sinks is not critical to how the circuit works, because it will all cancel out, as long as the FETs are matched and the resistors are identical). The resulting \$V_{GS}\$ is -2.8V (note that the gate is tied to -15V). This is the same voltage dropped across the resistor: \$V_{RESISTOR} = -V_{GS}\$. Again, this exact value is not critical, it could have been -2.5V, or -3.5V, etc.

We don't know yet the voltage of its drain (which is the same as \$V_{OUT}\$).

The top FET must also be conducting 2mA, and since it is identical to the bottom FET, then we know its \$V_{GS} = -2.8V\$.

So \$V_{IN}\$ first goes up one \$-V_{GS}\$ (we're at its source now, and I say "up" because we're subtracting a negative number, so the actual voltage goes "up"), and comes back down the same amount because of the resistor, that must be dropping the same voltage as the bottom resistor (because they share the same current), which we know is equal to \$V_{GS}\$.

In summary: $$V_{OUT} = V_{IN}-V_{GS}-V_{RESISTOR} $$ $$V_{OUT} = V_{IN}-V_{GS}-(-V_{GS})$$ $$\therefore V_{OUT} = V_{IN}$$

So there you go.

PS: Note that there was a typo in the book, because it says that the source of the upper FET is \$V_{IN}+V_{GS}\$, but this is not exactly true: $$V_{S} = V_{S}+(V_{G}-V_{G})$$ $$V_{S} = (V_{S}-V_{G})+V_{G}$$ $$V_{S} = V_{SG}+V_{G}$$ $$V_{S} = V_{G}-V_{GS} $$ $$\therefore V_{S} = V_{IN}-V_{GS}$$

As a final remark, note that the output impedance is now 1.4k, instead of 1/gm for the simpler source follower with Rs, so the next stage should have an input impedance of at least a few tens of k's. Analyzing this circuit for bandwidth would be an interesting exercise.

  • \$\begingroup\$ The circuit looks like buffer isn't it? \$\endgroup\$ – Unknown123 Mar 15 '18 at 7:40

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