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I study cache memories. I'm supposed to calculate the data hit rate for a function call with a 1024 byte direct mapped data cache and block size 16 byte. …

My cache can have 32 address bits with 2 bits for index and 3 bits for byte-offset. Associativity 2, block size 8. Of course, the the bits for index says which row of the cache the data is. …

If a cache memory has associativity 4, then it means than the memory has "4 blocks per set" but how do I visualize it? … It "4 blocks per set" the same as "4 blocks per row" so that a cache memory with associativity 4 and 10 sets will have 40 blocks, 4 per row or did I misunderstand? …

For a certain cache, these are the measurements: Test of different sizes of cache memory, from 16 to 1024 words, Block size = 2 words and assosiativity = 1. Access time: 20 cycles. …

I vary the D-cache block size for a program. I test different block sizes for the D-cache, block sizes from 1 to 8. Size = 128 words, and blocks in sets (associativity) = 1. …

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. …

I'm learning the logic of cache memories. I wonder if you can verify that I understood correctly. … If a cache memory in the tag field has 16 bits, the set field has 10 bits and the byte in block field is 6 bits, then I can deduce from only that information that the capacity is 128 kbyte and it is 2- …

We're simulating a MIPS cache with a program called MipsIT. We've reached a point where we should set access time for the memory. But I don't understand how to calculate this setting. … It says in the spec Reset the simulator and make sure that I-cache and D-cache are enabled. Set a reasonable access time for the primary memory. …

I've a difficulty understanding what is asked by this questions: Can you explain in more detail? AFAIK the associativity determines the number of sets and the size of the set determines the number …

It also has a small data cache capable of holding eight 32-bit words, where each cache line contains only two words. Consider a direct-mapped cache. … Answer Since the cache is direct-mapped, the size of the set is 256 bits (?) = 32 byte and therefore it takes 5 bits to address the memory, so the number of bits that are not the tag is 5 (?) …

If I assume that the first element of the matrix that is fetched to the D-cache is a[0][0], for associativity 4, please tell me which element in which matrix that will write over a[0][0] in the D-cache … Since the formula for set associativity is In a set-associative cache, the set containing a memory block is given by (Block number) modulo (Number of sets in the cache) How can I know from this …

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. …

AFAIK this definition is the most clear and physical: Associativity number = Number of comparators. Is it correct? Could you make a more precise / better definition? The wikipedia illustration is …

I have a cache memory simulator with this cache memory shown. The cache size is 64 bytes and the block size is 8 bytes. What is the decomposition into fields? …

I understand a cache memory is constructed for a basic block like this Valid bit | Address bits | Data/Instruction But what determines the length of the address bits? …