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Mitu Raj
Mitu Raj
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I have a somewhat stupid question as I am still a noob. So bear with me.

ifIf I have the following statement in Verilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

I have a somewhat stupid question as I am still a noob. So bear with me.

if I have the following statement in Verilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

I have a somewhat stupid question as I am still a noob. So bear with me.

If I have the following statement in Verilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

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Mitu Raj
Mitu Raj
  • 11k
  • 6
  • 25
  • 48

synthesis Synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me.

if I have the following statement in verilogVerilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the dD flip flop-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me.

if I have the following statement in verilog

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the d flip flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

Synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me.

if I have the following statement in Verilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

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hardware noob
hardware noob
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synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me.

if I have the following statement in verilog

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the d flip flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?