Parallel trace signal integrity: Increasing width to match characteristic impedance vs increasing trace gap

Question

Imagine you are routing a large number of single ended high speed traces through a long narrow gap on a PCB. Lets say these are ultra-high speed SD signals, so a 208MHz clock. The traces should be 50mil to match the impedance of the source and receiver.

However, as you are short on space you have to choose one of the two options:

1. Route at the correct width for impedance matching, at a cost of reducing your inter-trace gap to 10mil (i.e. 0.2W), thus greatly increasing crosstalk
2. Route at 10mil width to achieve a larger gap of 50mil (i.e. 5W), at a cost of a significant impedance mismatch.

Which of these two options is the lesser evil and why? If the answer is somewhere in the middle, how do you evaluate the tradeoff? Does there exist any rules of thumb for prioritising characteristic impedance vs crosstalk?

Answer 1

Option c: use a thinner dielectric layer so that a 10 mil trace matches 50 ohms.